Homedatasheet11C06

11C06 Datasheet

750 MHZ D-type Flip-flop (obsolete)
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Description

Features, Applications

The is a high-speed ECL D-Type Master-Slave FlipFlop capable of toggle rates over 750 MHz Designed primarily for high-speed prescaling it can also be used in any application which does not require preset inputs The circuit is voltage-compensated which makes input thresholds and output levels insensitive to VEE variations Complementary Q and Q outputs are provided as are two Data inputs Clock and Clock Enable inputs The 11C06 is pin-compatible with the Motorola MC1690L but is a higher-frequency replacement

Pin Names CE Q Description Data Input Clock Input Clock Enable (Active LOW) Outputs H Qnb1

H e HIGH Voltage Level L e LOW Voltage Level X e Don't Care L e LOW to HIGH Transition Qnb1 e Previous State

Above which the useful life may be impaired If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Maximum Junction Temperature (TJ) Supply Voltage Range Input Voltage (DC) Output Current (DC Output HIGH)

Min Supply Voltage (VEE) Ambient Temperature (TA)
Conditions VIN e VIH (Max) or VIL (Min) per Truth Table Loading to b2V

Guaranteed Input Voltage HIGH for All Inputs Guaranteed Input Voltage LOW for All Inputs VIN e VIH (Max)

Input Current HIGH Clock Input Data Input Current LOW Power Supply Current 05

VEE b5 2V VCC e GND 25 C Symbol tPHL tPLH tTLH tTHL tS tH fTOG (MAX) Parameter Propagation Delay (CP-Q) Propagation Delay (CP-Q) Transition Time to 80% Transition Time to 20% Set-up Time Hold Time Toggle Frequency (CP) 650 Min Typ Max Units ns MHz See Figure 2 Note See Figure 1 Conditions

Note The device is guaranteed for fTOG (CP) t 600 MHz fTOG(CE) t 550 MHz over the 75 C temperature range

While the clock is LOW the slave is held steady and the information on the D input is permitted to enter the master The next transition from LOW to HIGH locks the master in its present state making it insensitive to the D input This transition simultaneously connects the slave to the master causing the new information to appear on the outputs Master and slave clock thresholds are internally offset in opposite directions to avoid race conditions or simultaneous master-slave changes when the clock has slow rise or fall times The CP and CE inputs are logically identical but physical constraints associated with the Dual-In-Line package make the CE input slower at the upper end of the toggle range To prevent new data from entering the master on the next CP LOW cycle CE should go HIGH while CP is still HIGH

e 50X termination of scope e 50X impedance lines All input transition times are 2 ns

e 50X termination of scope e 50X impedance lines Adjust VBIAS for 0 7V baseline 800 mV peak-to-peak sinewave input All input transition times are 2 ns


Features

Parameters

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Manufacturer information

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