Homedatasheet430HXPCIset

430HXPCIset Datasheet

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Features, Applications

Superior DRAM Data Integrity Single Bit Error Correction, Multi-Bit Error Detection plus Nibble Failure Detection ECC Code Single and Multi-Bit Error Reporting Virtual Swapable Bank Support (i.e., can swap out problem banks) Merging Write Buffer Eliminates Most Partial Writes Cycles

Supports All 3V Pentium � Processors Dual Processor Support PCI 2.1 Compliant Integrated Second-Level Cache Controller

Direct Mapped Organization Write-Back Cache Policy Cacheless, 256 KB, and 512 KB Pipelined Burst SRAMs Cache Hit Read/Write Cycle Timings at 3-1-1-1 Back-to-Back Read Cycles at 3-1-1-1-1-1-1-1 Integrated Tag/Valid Status Bits for Cost Savings and Performance Optional 512-MB DRAM Cacheability Limit Supports 5V SRAMs for Tag Address

to 512-MB Main Memory 64-Mb DRAM Technology Support 8-QWord Deep Merging DRAM Write Buffer Enhanced EDO/Hyper Page Mode DRAM; 4-2-2-2 Reads and x-2-2-2 Writes at 60 MHz; 5-2-2-2 Reads and x-2-2-2 Writes at 66 MHz 8 RAS Lines Integrated Programmable-Strength Memory Address Buffers CAS-Before-RAS Refresh

Zero Wait State CPU-to-PCI Write Timings (no IRDY stall) for Superior Graphics Performance Enhanced CPU-to-PCI Read Latencies for Superior Graphics/PIO Performance 21-DWord PCI-DRAM Post Buffer 22-DWord PCI-to-DRAM Read Prefetch Buffer Write-Back Merging for PCI to DRAM Writes Write-Back Forwarding for PCI to DRAM Reads Pipelined Snoop Ahead Multi-Transaction Timer to Support Multiple Short PCI Transactions Within the Same PCI Arbitration Cycle

Supports the Universal Serial Bus (USB) Supported Kits

The Intel 430HX PCIset consists of the 82439HX System Controller (TXC) and the 82371SB PCI I/O IDE Xcelerator (PIIX3). The TXC is a single-chip host-to-PCI bridge and provides the second level cache control and DRAM control functions. The second level (L2) cache controller supports a write-back cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory is implemented with synchronous pipelined burst SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. The TXC provides a 64/72-bit data path to main memory and memory sizes to 512 Mbytes. The DRAM controller provides eight rows and optional DRAM Error detection/correction or parity. The TXC's optimized PCI interface allows the CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop ahead feature, The TXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the TXC contains read prefetch and posted write buffers.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 430HX PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners.

Host Interface PCI Interface AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# STOP# LOCK# DEVSEL# PAR REQ[3:0]# GNT[3:0]# PHLDA# PHLD# SERR# MAA[1:0] MAB[1:0] MWE# HCLKIN PCLKIN RST# TEST#

BE[7:0]# ADS# D/C# M/IO# W/R# BRDY# EADS# HITM# BOFF# AHOLD NA# KEN#/INV CACHE# HLOCK# SMIACT#
CCS# TWE# COE# GWE# CADS# CADV# TIO[7:0] TIO[10:8] BWE

REVISION HISTORY...................................................................................................................................... 4 1.0. ARCHITECTURE OVERVIEW................................................................................................................. 5 2.0. SIGNAL DESCRIPTION.......................................................................................................................... 7 2.1. Host Interface....................................................................................................................................... 7 2.2. DRAM Interface................................................................................................................................... 8 2.3. Secondary Cache Interface.................................................................................................................. 9 2.4. PCI Interface...................................................................................................................................... 10 2.5. Clock, Reset, and Test....................................................................................................................... 11 3.0. REGISTER DESCRIPTION................................................................................................................... 12 3.1. I/O Control Registers.......................................................................................................................... 12 3.1.1. CONFADDCONFIGURATION ADDRESS REGISTER............................................................ 12 3.1.2. CONFDATACONFIGURATION DATA REGISTER.................................................................. 13 3.2. PCI Configuration Space Mapped Registers...................................................................................... 14 3.2.1. PCI CONFIGURATION ACCESS................................................................................................ 14 3.2.2. VIDVENDOR IDENTIFICATION REGISTER........................................................................... 15 3.2.3. DIDDEVICE IDENTIFICATION REGISTER............................................................................. 16 3.2.4. PCICMDPCI COMMAND REGISTER...................................................................................... 16 3.2.5. PCISTSPCI STATUS REGISTER............................................................................................ 17 3.2.6. RIDREVISION IDENTIFICATION REGISTER......................................................................... 17 3.2.7. CLASSCCLASS CODE REGISTER........................................................................................ 18 3.2.8. MLTMASTER LATENCY TIMER REGISTER.......................................................................... 18 3.2.9. HEADTHEADER TYPE REGISTER........................................................................................ 19 3.2.10. BISTBIST REGISTER............................................................................................................ 19 3.2.11. ACONARBITRATION CONTROL.......................................................................................... 19 3.2.12. PCONPCI CONTROL............................................................................................................ 20 3.2.13. CCCACHE CONTROL REGISTER........................................................................................ 21 3.2.14. DRAMECDRAM EXTENDED CONTROL REGISTER........................................................... 22 3.2.15. DRAMCDRAM CONTROL REGISTER.................................................................................. 23 3.2.16. DRAMTDRAM TIMING REGISTER....................................................................................... 23 3.2.17. PAMPROGRAMMABLE ATTRIBUTE MAP REGISTERS 25 3.2.18. DRBDRAM ROW BOUNDARY REGISTERS......................................................................... 27 3.2.19. DRTDRAM ROW TYPE REGISTER...................................................................................... 29 3.2.20. SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER.......................................... 29 3.2.21. ERRCMDERROR COMMAND REGISTER............................................................................ 31 3.2.22. ERRSTSERROR STATUS REGISTER................................................................................. 32 3.2.23. ERRSYN ERROR SYNDROME REGISTER......................................................................... 33


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