In-System Programmable 3.3V SuperWIDETM High Density PLD Features
SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 3.3V Power Supply User Selectable 3.3V/2.5V I/O 18,000 PLD Gates / 384 Macrocells to 288 I/O Pins 384 Registers High-Speed Global Interconnect SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. PCB Efficient Ball Grid Array (BGA) Package Options Interfaces with Standard 5V TTL Devices HIGH PERFORMANCE E2CMOS� TECHNOLOGY fmax = 125 MHz Maximum Operating Frequency tpd 7.5 ns Propagation Delay Enhanced = 7 ns, 3.5ns TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels Electrically Erasable and Reprogrammable Non-Volatile Programmable Speed/Power Logic Path Optimization IN-SYSTEM PROGRAMMABLE Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE ARCHITECTURE FEATURES Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs Wrap Around Product Term Sharing Array Supports to 35 Product Terms Per Macrocell Macrocells Support Concurrent Combinatorial and Registered Functions Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks Slew and Skew Programmable I/O (SASPI/OTM) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell ispDesignEXPERTTM � LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM PC and UNIX Platforms
The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and five extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.comFigure 1. ispLSI 5384VA Functional Block Diagram (388 BGA Option)
CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is determined by the package type used � see table below. Package Type 208 PQFP 208 fpBGA 272 BGA 388 BGA I/O / CLK2 I/O / CLK2 I/O / CLK2 I/O / CLK2 Multplexed Signals I/O / CLK3 I/O / CLK3 I/O / CLK3 I/O / CLK3 I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE
The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The five extra product terms are used for shared GLB controls, set, reset, clock, clock enable and output enable. The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, which can be fed back through the Global Routing Pool. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. Reset and preset for the macrocell register is provided from both global and product term signals. The macrocell register can be programmed to operate as a Dtype register, a D-type latch or a T-type flip flop. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one line from each macrocell output and one line from each I/O pin. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink in 3.3V mode. The output drivers have Table 1. ispLSI 5000VA Family a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows the output drivers to drive either or 2.5V output levels while the device logic and the output current drive is always powered from 3.3V. The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs and a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. The ispLSI 5000V Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.
The ispLSI 5000V Family ranges from 256 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000VA Family device matrix showing the various bondout options is shown in the table below. The interconnect structure (GRP) is very similar to Lattice's existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool.
Package Type Device ispLSI 5256VA ispLSI 5384VA ispLSI 5512VA GLBs 12 16 Macrocells fpBGA 144 I/O 144 I/O 208 PQFP 144 I/O 144 I/O 144 I/O 272 BGA 192 I/O 192 I/O 192 I/O 388 BGA 288 I/O 288 I/O