Homedatasheet54F190

54F190 Datasheet

Military/Aerospace->FAST
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Description

Features, Applications
74F190 Up Down Decade Counter with Preset and Ripple Clock
74F190 Up Down Decade Counter with Preset and Ripple Clock

The is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting The preset feature allows the to be used in programmable dividers The Count Enable input the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters In the counting modes state changes are initiated by the rising edge of the clock

Features

High-speed 125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable

Package Description (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line (0 150 Wide) Molded Small Outline JEDEC 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C

Note 1 Devices also available in 13 reel Use suffix e SCX

Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH)

The is a synchronous up down BCD decade counter containing four edge-triggered flip-flops with internal gating and steering logic to provide individual preset count-up and count-down operations It has an asynchronous parallel load capability permitting the counter to be preset to any desired number When the Parallel Load (PL) input is LOW information present on the Parallel Data inputs P3) is loaded into the counter and appears on the Q outputs This operation overrides the counting functions as indicated in the Mode Select Table A HIGH signal on the CE input inhibits counting When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input The direction of counting is determined by the U D input signal as indicated in the Mode Select Table CE and U D can be changed with the clock in either state provided only that the recommended setup and hold times are observed RC Truth Table Inputs CP X Output RC H

Two types of outputs are provided as overflow underflow indicators The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the countdown mode or reaches 9 in the count-up mode The TC output will then remain HIGH until a state change occurs whether by counting or presetting or until D is changed The TC output should not be used as a clock signal because it is subject to decoding spikes The TC signal is also used internally to enable the Ripple Clock (RC) output The RC output is normally HIGH When CE is LOW and TC is HIGH the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again This feature simplifies the design of multistage counters For a discussion and illustrations of the various methods of implementing multistage counters please see the 'F191 data sheet Mode Select Table Inputs CE CP Count Up Count Down Preset (Asyn ) No Change (Hold) Mode

TC is generated internally H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition e LOW Pulse

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays


Features

Parameters


Manufacturer information

Warm Hint

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