74LVC125APW Datasheet

Logic - Buffers, Drivers, Receivers, Transceivers


The 74LVC125APW is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. The 74LVC125APW consists of four non-inverting buffers/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high impedance OFF-state. 74LVC125APW Features • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic• Supply voltage range of 1.2V to 3.6V• Complies with JEDEC standard no. 8-1A• CMOS low power consumption• Direct interface with TTL levels• High impedance when VCC = 0V


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Manufacturer information

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