Homedatasheet3D7502D-25

3D7502D-25 Datasheet

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Features, Applications

FEATURES

All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Maximum data rate: 50 MBaud Data rate range: �15%

The 3D7502 product family consists of monolithic CMOS Manchester RX Signal Input Decoders. The unit accepts at the RX input a bi-phase-level, CLK Signal Output (Clock) embedded-clock signal. In this encoding mode, a logic one is DATB Signal Output (Data) represented by a high-to-low transition within the bit cell, while a logic VCC +5 Volts zero is represented by a low-to-high transition. The recovered clock GND Ground and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as �15% from the nominal device baud rate without compromising the integrity of the information received. Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off. The all-CMOS 3D7502 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Decoders. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14pin SOICs.

BAUD RATE (MBaud) Nominal Minimum Maximum
NOTES: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost.

The 3D7502 Manchester Decoder samples the input at precise pre-selected intervals to retrieve the data and to recover the clock from the received data stream. Its architecture comprises finely tuned delay elements and proprietary circuitry which, in conjunction with other circuits, implement the data decoding and clock recovery function.

The 3D7502 presents at its outputs the decoded data (inverted) and the recovered clock. The decoded data is valid at the rising edge of the clock. The clock recovery function operates in two modes dictated by the input data stream bit sequence. When a data bit is succeeded by its inverse, the clock recovery circuit is engaged and forces the clock output low for a time equal to one over twice the baud rate. Otherwise, the input is presented at the clock output unchanged, shifted in time. When engaged, the clock recovery circuit generates a low-going pulse of fixed width. Therefore, the clock duty cycle is strongly dependent on the baud rate, as this will affect the clock-high duration. The clock output falling edge is not operated on by the clock recovery circuitry. It, therefore, preserves more accurately the clock frequency information embedded in the transmitted data. Therefore, it can be used, it is desired, to retrieve clock frequency information.

Encoded data transmitted from a source arrives at its destination corrupted. Such corruption of the received data manifests itself as jitter and/or pulse width distortion at the input to the device. The instantaneous deviations from nominal Baud Rate and/or Pulse Width (high or low) adversely impact the data extraction and clock recovery function if their published limits are exceeded. See Table 4, Allowed Baud Rate/Duty Cycle. The 3D7502 Manchester Decoder Data Input is TTL compatible. The user should assure himself that the 1.5 volt TTL threshold is used when referring to all timing, especially the input pulse widths.

The 3D7502 Manchester Decoder, being a selftimed device, is tolerant of frequency modulation (jitter) present in the input data stream, provided that the input data pulse width variations remain within the allowable ranges.

CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D7502 Manchester Decoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature.

PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN MAX 150 300 UNITS mA C NOTES

to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL & TF MIN MAX 40 UNITS mA ns NOTES

*IDD(Dynamic) 2 * CLD * VDD * F where: CLD = Average capacitance load/pin (pf) F = Input frequency (GHz)

Input Capacitance 10 pf typical Output Load Capacitance (CLD) 25 pf max

to 5.25V, except as noted) PARAMETER Nominal Input Baud Rate Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Duty Cycle Bit Cell Time Input Data Edge to Clock Falling Edge Clock Width Low Clock Falling Edge to Data Transition


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