Homedatasheet5962-8552801RA

5962-8552801RA Datasheet

CMOS Bus Arbiter
Share:
Manufacturer

Description

Features, Applications

Description

The Intersil 82C89 Bus Arbiter is manufactured using a selfaligned silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the 82C88 bus controller, provides full bus arbitration and control for multi-processor systems. The 82C89 is typically used in medium to large or 80C88 systems where access to the bus by several processors must be coordinated. The 82C89 also provides high output current and capacitive drive to eliminate the need for additional bus buffering. Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in performance equal to or greater than existing equivalent products at a significant power savings.

Features

Pin Compatible with Bipolar 8289 Performance Compatible with: - 80C86/80C88.(5/8MHz) Provides Multi-Master System Bus Control and Arbitration Provides Simple Interface with 82C88/8288 Bus Controller Synchronizes 80C86/8086, 80C88/8088 Processors with Multi-Master Bus Bipolar Drive Capability Four Operating Modes for Flexible System Configuration Low Power Operation - ICCSB. 10�A (Max) - ICCOP.1mA/MHz (Max) Operating Temperature Ranges to +125oC

PART NUMBER MR82C89/B 5962-85528012A SMD# 20 Pad CLCC SMD# 20 Ld CERDIP 20 Ld PLCC PACKAGE 20 Ld PDIP TEMPERATURE RANGE to +125oC PKG. NO. F20.3 J20.A

S2 IOB SYSB/RESB RESB BCLK INIT BREQ BPRO BPRN VCC S0 17 CLK 16 LOCK INIT 15 CRQLCK BREQ 14 ANYRQST 13 AEN 12 CBRQ 11 BUSY BPRO BPRN 10 GND 11 BUSY 12 CBRQ 13 AEN RESB BCLK S0 17 CLK 16 LOCK 15 CRQLCK 14 ANYRQST

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999

INIT BCLK BREQ BPRN BPRO BUSY CBRQ

PIN SYMBOL VCC NUMBER 20 TYPE DESCRIPTION VCC: The +5V Power supply pin. A 0.1�F capacitor between pins 10 and 20 is recommended for decoupling. GROUND. I STATUS INPUT PINS: The status input pins from or 8089 processor. The 82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1). CLOCK: From the or 82C85 clock chip and serves to establish when bus arbiter actions are initiated. LOCK: A processor generated signal which when activated (low) prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter, regardless of its priority. COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin. RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is requested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB input is ignored. ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered to a lower priority arbiter if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon it is possible). When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Information. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to surrender the multi-master system bus after each transfer cycle. Note that when surrender occurs BREQ is driven false (high).

DESCRIPTION IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both an IO Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders the use of the multi-master system bus as a function of the status line, S2. The multi-master system bus is permitted to be surrendered while the processor is performing IO commands and is requested whenever the processor performs a memory command. Interrupt cycles are assumed as coming from the peripheral bus and are treated an IO command. ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor's address latches, to the 82C88 Bus Controller and or 82C85 Clock Generator. AEN serves to instruct the Bus Controller and address latches when to three-state their output drivers. INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters on the multi-master system bus. After initialization, no arbiters have the use of the multi-master system bus. SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Resident Mode (RESB is strapped high) which determines when the multi-master system bus is requested and multi-master system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping circuitry, such as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are permitted on this pin from T2 of the processor cycle. During the period from of T4, only clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it, and the multi-master system bus may be requested or surrendered, depending upon the state of the glitch. The arbiter requests the multi-master system bus in the System/Resident Mode when the state of the SYSB/RESB pin is high and permits the bus to be surrendered when this pin is low. COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbiters of lower priority requesting the use of the multi-master system bus. The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multimaster system bus upon request are connected together. The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any other arbiter connected to the CDRQ line can request the multi-master system bus. The arbiter presently running the current transfer cycle drops its BREQ signal and surrenders the bus whenever the proper surrender conditions exist. Strapping CBRQ low and ANYRQST high allows the multi-master system bus to be surrendered after each transfer cycle. See the pin definition of ANYRQST.

BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface signals are synchronized. BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the arbiter activates to request the use of the multi-master system bus. BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the multi-master system bus on the next falling edge of BCLK. BPRN active indicates to the arbiter that it is the highest priority requesting arbiter presently on the bus. The loss of BPRN instructs the arbiter that it has lost priority to a higher priority arbiter. BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme where BPRO is daisy-chained to BPRN of the next lower priority arbiter. BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the arbiters on the bus when the multi-master system bus is available. When the multi-master system bus is available the highest requesting arbiter (determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of the bus. When the arbiter is done with the bus, it releases the BUSY signal, permitting to go high and thereby allowing another arbiter to acquire the multimaster system bus.


Features

Parameters

Download DataSheet PDF View and Download


Manufacturer information

Warm Hint

What HQEW.NET can offer here?
1. www.hqew.net/product-data provides numerous and various electronic part data-sheet and technology document here., if it can't be shown, Please feel free to ask us for it.
2. www.hqew.net/news provides the latest information of the semiconductor industry or the electronics industry for you.
3. www.hqew.net provides verified suppliers and numerous electronic components for your demand and business.
Any questions you can contact us by email cs@hqew.net.
related datasheet
Browse Alphabetically: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9
Contact Us

+86-755-83536845

One to One Customer Service

17190417227