5962-8765601SA Datasheet



Features, Applications

The 'FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.


Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous Master Reset See 'FCT377 for clock enable version See 'FCT373 for transparent latch version See 'FCT374 for TRI-STATE � version Output sink capability of 32 mA, source capability mA n TTL input and output level compatible n CMOS power consumption n Standard Microcircuit Drawing (SMD) 5962-8765601

Military W20A E20A Package Number 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description

TRI-STATE is a registered trademark of National Semiconductor Corporation.

Description Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs

Operating Mode MR Reset (Clear) Load "1" Load L H Inputs h l Output H L

H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial N = LOW-to-HIGH clock transition

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State +5.0 mA

Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current -500 mA (Across Comm Operating Range) Over Voltage Latchup VCC + 4.5V

Free Air Ambient Temperature Military Supply Voltage Military to +5.5V

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Symbol VIH VIL VCD VOH VOL IIH IIL IOS ICCQ ICC ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 54FCT FCT240 Min 0.8 -1.2 Max Units �A mA Min Max VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN -18 mA IOH -300 uA IOH -12 mA IOL 300 �A IOL 32 mA VIN = 5.5V VIN = 0.0V VOUT = 0.0V VIN 0.2V or VIN = 5.3V VIN = 3.4V VIN 3.4V or VIN = GND, OE = GND, = 10Mhz, outputs open, one bit toggling - 50% duty cycle VIN 5.3V or VIN 0.2V,OE = GND, = 10Mhz, outputs open, one bit toggling - 50% duty cycle Outputs Open,OE = GND, One Bit Toggling, 50% Duty Cycle

Input HIGH Current Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current Total Power Supply Current

Symbol Parameter to +125�C VCC 50 pF Min tPLH tPHL Propagation Delay to On Propagation Delay On 2.0 Max 15.0 ns Units Fig. No.



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