The is a discrete-to-digital interface device. The inputs have been designed to handle 28 V/Gnd, 28 V/Open, and Open/Gnd signals. The device can also be configured as either a 32 triple-redundant or 96 nonredundant discrete input with either a microprocessor and/or ARINC 429 output. The device can be HIRF protected by adding capacitors to the input resistor network. The device uses comparators in a triple-redundant configuration to take a consensus of the input state and raise a flag when there is no consensus. The device's microprocessor output is an addressable or 16bit tri-state port, which selects channel data, status, bounce, built-in-selftest (BIST) and major fault. All are compatible with TTL logic.APPLICATIONS
The design specifically addresses redundancy, built-in self-test autonomy, fault isolation and tolerance at the chip level. In the 96-channel mode the device loses the capability of taking consensus of the input states as well as mismatch. These features are tripleredundant configuration specific. All other features are still available. These features, along with high-reliability and low cost, enable the device to serve a variety of interface requirements in aerospace applications, including flight critical, essential and non-essential functions. The optional ARINC 429 output port is particularly well-suited to data concentrator requirements.FEATURES
28 V/Gnd Open/Gnd, 28 V/Open Input Resistor Usage
5 ENABLE HI ENABLE LO 5 DISCRETE DATA EN ARINC DATA EN DISCRETE DATA TRANSFER VERIFIER
TRANSFER FAULT BIT TRANSFER FAULT PROCESSING CIRCUITRY
TRI-STATE ENABLES ARINC 429 XMITTER READY 10uS CLOCK 80uS CLOCK 2
TABLE 1. DD-03201 SPECIFICATION PARAMETER ABSOLUTE MAXIMUM RATINGS Supply VoItages (VDD) Analog Inputs Digital Inputs OPERATING CONDITIONS Supply Voltages (VDD) DIGITAL INPUTS/OUTPUTS Logic Compatibility Digital Inputs
TABLE 1. DD-03201 SPECIFICATION TYP 5.0 MAX VDD+0.3 5.5 PHYSICAL CHARACTERISTICS Size Weight in. (mm) oz. (g) 1.0 26.0 PARAMETER MTBF per MIL-Hbk 217 for airborne Inhabited Cargo at 64�C UNITS MlN TYP MAXClock Inputs (See Note 1) Digital Outputs
Note: For the ARINC 429 option the bit rate is derived from the clock. Refer to ARINC 429 Bit Rate to avoid interference. ARINC 429-14 (January 4, 1993), paragraph 2.4,: "Timing Related Elements" contains a "Commentary" section following subparagraph 18.104.22.168 ("Low Speed Operation") that cautions against using "precisely" 100 kilobits per second.
Advisory Circular (FAA), Airworthiness Approval of Traffic Alert and Collision Avoidance Systems (TCAS II) and Mode S Transponders, AC20-131, defines a discrete as "a separate, complete and distinct signal. " In many instances these signals are binary, on or off, 28 V-based signals; they are typically Open/Gnd, 28 V/Open, or 28 V/Gnd with very low bandwidth (DC to 200 Hz). While on the surface the translation of these signals to TTL-levels compatible with digital avionics may seem simple, RTCA DO-160C power, lighting and high-intensity-radiated-fields (HIRF) are complicating factors. Add to that the desire to have a standardized, addressable, reliable interface and the challenge becomes apparent. Today's systems address the interface with circuits tailored for each interface comprised of R-C input filters, divider networks, diode isolation and comparators. Multichannel interface to a processor requires additional logic and latches. The resulting circuit generally lacks any built-in test capability, consumes considerable pc-board real estate (up to one sq. in. per channel), and offers no chip-level redundancy.ANALOG INPUTS Analog Inputs s Input currents: Input channels Reference inputs Self-test inputs
Input channel and corresponding reference input POWER SUPPLY REQUIREMENTS (Total VDD, Analog & Digital) IDD (VDD = +5V [Digital Outputs Unloaded]) POWER DISSIPATION PD THERMAL Operating Temperature
Using the aggregated definition and functional requirements of industry, ILC Data Device Corporation has developed a programmable 32/96-channel discrete interface with inputs capable of handling 28 V/Open, Open/Gnd and 28 V/Gnd signals. When using the 32-channel mode, the design uses comparators in a triple-redundant configuration, so that each channel will take a consensus of the input state, and raise a flag when there is no consensus (concensus fails).The device's output is a selectable or 16-bit tri-state port, which can be addressed for channel data, status, bounce, built-in-self-test and major fault information. This design specifically addresses built-in self-test autonomy, fault isolation and tolerance; moreover, its functional integration
Storage Temp Lead Temperature (Localized, 1 sec. duration) (Body, 2 sec. duration) Junction Temperature jc ca
results in significant added reliability. A comparative look at MTBF calculated in accordance with MIL-HBK-217 for airborne inhabited cargo environments at 64�C indicates an order of magnitude improvement for an integrated approach vs. a similarly packaged discrete-component implementation. Moreover, the real estate is reduced from 32 square inches to 1.21 square inches for a 32-channel and from 64 square inches to 1.21 square inches for the 96-channel device. Additional key features include:
The DD-03201 is configured with either a 16-bit microprocessor. FIGURE 2 illustrates this interface. The read cycle(s) should be preceded by polling the device's READY bit which is located within the Status Register. The Status Register can be read at any time regardless of the state of the READY signal (pin 150) from the device. If the READY bit is a logic "1" (this can be easily tested by a branch if negative statement) the address of the desired register, along with the negative true ENABLE signal, should be presented to the device. The additional data will be available within 100 nsec. After the data is read the ENABLE line should be returned to a logic "1" level. All of the data within the device is guaranteed to remain stable for at least 20 �sec after the high-to-low transition of the READY signal (See FIGURE 3).
parators are physically located on three different edges of the custom chip so that an edge failure is not catastrophic.
FAULT TOLERANCE: In 32-channel mode, a single comparator failure is reported as a mismatch or BIT fault, but does not result in a hard-failure. BOUNCE: Relays and switches, as mechanical devices, have a characteristic `bounce' to their signal transition. It is desirable to mask this bounce by delaying the output digital transition accordingly. This sampling rate of the device can be varied to allow for debounce of relay/switch inputs. In addition, the triple sampling of a given comparator enables a consistent reading of otherwise asynchronous signals. Bounce is an addressable register that allows the user to detect bouncing or intermittent relays/switches. REGISTERS: or 16-bit selectable data or status is available
FIGURE 4 illustrates the architecture of the analog input and front-end self-test circuits. Each group of 32-channels (A, B and C groups) are identically configured, with REF_A setting the threshold for the `A' group of comparators, REF_B setting the threshold for the `B' group, etc. During the self-test portion of each cycle, the comparator inputs are switched from the NORMAL to the TEST position, an alternating 1/0 (HI/LO) pattern is applied to each group of comparators and a functional test is performed. The test is then repeated with an alternating 0/1 (LO/HI) pattern.
OPTIONAL ARINC 429 PORT: A serial ARINC 429 output is available for data concentrator applications. This enables the transfer of data to other systems with a minimum of wiring and processor loading. TEST PATTERNS: Internal Test Patterns can be selected to produce alternating `1's and `0's to verify that all address and data bits are operational. These outputs are always available, regardless of READY state. They must be addressed by the user A0) in accordance with TABLES 3 and 4. DISSIMILAR PATHS: Errors are reported through registers and
DEFERRED MAINTENANCE: The error reporting scheme differentiates soft- and hard-failures to allow continued operation despite failures. INTELLIGENCE: The device's built-in self-test, status reporting
INPUT CHANNELS: (Pins and 99-114) Configured as three groups of 32-channels each; each group is associated with its own reference and self-test inputs. The device may be connected as 96-independent channels or 32-triple-redundant channels. Refer to FIGURE 5 and FIGURE 6 for a typical example of each configuration. For 32-channel operation, "Channel 1" drives the A1, B1 and C1 inputs, "Channel 2" drives the A2, B2 and C2 inputs, and so forth. The example in FIGURE 5 shows redundant input networks that provide isolation between ASIC input pins and protect the two working channel sections in the event of a short from an ASIC input pin to ground or VDD on the third section. REFERENCE INPUTS: (Pins 39, 79 and 116) Each reference input sets the threshold voltage for the corresponding group of 32 comparators. SELF-TEST INPUTS: (Pins and 117) High and low self-test threshold settings. These settings should be set to at least 100 mV above (HI) and 100 mV below (LO) the reference (REF) input for the corresponding group of 32 comparators.
scheme and fault-tolerance/isolation significantly reduces application software requirements. FIGURE 1 illustrates the model DD-03201 functional block diagram.