IS42S16320B-7TLI-TR Datasheet



The 512Mb SDRAM(IS42S16320B-7TLI-TR/ IS42S16320B ) is a high speed CMOS, dynamic random-access memory designed to operate in 3.3VVdd and 3.3VVddq memory systems containing 536,870,912bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 134,217,728-bit bank is organized as 8,192 rows by 1024 columns by 16 bits. Each of the x8s 134,217,728-bit banks is organized as 8,192 rows by 2048 columns by 8 bits. The512MbSDRAMincludesanAUTOREFRESHMODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The512MbSDRAMhas theability tosynchronouslyburst data at a high data rate with automatic column-address generation,theabilitytointerleavebetweeninternalbanks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. IS42S16320B-7TLI-TR Features • Clock frequency: 166, 143, 133 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Self Refresh• 8K refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)• Random column address every clock cycle• Programmable CAS latency (2, 3 clocks)• Burst read/write and burst read/single write operations capability• Burst termination by burst stop and precharge command• Available in 54-pinTSOP-II and 54-ball W-BGA (x16 only)


[{"Name":"Data Bus Width:","Value":"16 bit"},{"Name":"Memory Size:","Value":"512 Mbit"},{"Name":" Maximum Clock Frequency:","Value":"143 MHz"},{"Name":" Access Time:","Value":"6.5 ns, 5.4 ns"},{"Name":"Supply Voltage - Max:","Value":"3.6 V"},{"Name":" Supply Voltage - Min:","Value":"3 V"},{"Name":"Maximum Operating Current:","Value":"130 mA"},{"Name":"Maximum Operating Temperature:","Value":"+ 85 C"},{"Name":" Minimum Operating Temperature:","Value":"- 40 C "},{"Name":"","Value":""}]

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