The a 2-Kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). The CAT24C02 is available in RoHS compliant "Green" and "Gold" 8-lead PDIP, SOIC, TSSOP and TDFN packages.
Supports Standard and Fast I2C Protocol 5.5 V Supply Voltage Range 16-Byte Page Write Buffer Hardware Write Protection for entire memory Schmitt Triggers and Noise Suppression FiltersLow power CMOS technology 1,000,000 program/erase cycles 100 year data retention RoHS compliant
For the location of Pin 1, please consult the corresponding package drawing.
A1, A2 SDA SCL WP VCC VSS Device Address Serial Data Serial Clock Write Protect Power Supply Ground
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS* Storage Temperature Voltage on Any Pin with Respect +6.5 V
* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(2) Symbol NEND(*) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years
D.C. OPERATING CHARACTERISTICS VCC to 85�C, unless otherwise specified. Symbol ICC ISB IL VIL VIH VOL1 VOL2 Parameter Supply Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC 2.5 V, IOL 3.0 mA VCC 1.8 V, IOL 1.0 mA Test Conditions Read or Write at 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max 1 2 VCC x 0.3 Units mAPIN IMPEDANCE CHARACTERISTICS = 400 kHz, VCC 5 V Symbol CIN(2) ZWPL ILWPH
Note: (1) The DC input voltage on any pin should not be lower than V or higher than VCC 0.5 V. During transitions, the voltage on any pin may undershoot to no less than V or overshoot to no more than VCC 1.5 V, for periods of less than 20 ns. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods.
Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Low Impedance WP Input High Leakage2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
A.C. CHARACTERISTICS VCC to 85�C, unless otherwise specified. 5.5 V Symbol FSCL tAA(2) tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF(1) tSU:STO tDH tWR tPU(1), (3)
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) For timing measurements the SDA line capacitance ~ 100 pF; the SCL input is driven with rise and fall times < 50 ns; the SDA I/O is pulled-up 3 mA current source; input driving signals swing from 80% of VCC. Output level reference levels are 30% and respectively 70% of VCC. (3) tPU is the delay required from the time VCC is stable until the device is ready to accept commands.
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Time the Bus Must be Free Before a New Transmission Can Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time Power-up to Ready Mode
Power-On Reset (POR) The CAT24C02 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The CAT24C02 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against `brown-out' failure following a temporary loss of power. The POR circuitry triggers at the minimum VCC level required for proper initialization of the internal state machines. The POR trigger level automatically tracks the internal CMOS device thresholds, and is naturally well below the minimum recommended VCC supply voltage.2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice