CD4017 product image

CD4017

Counter/Dividers
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Manufacturer
Texas Instruments
FAIRCHILD Semiconductor
Description

 

CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and tall times.

These counters are advances one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CD4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.

 

CD4017 Features

 

  • •Fully static operation
  • •Medium-speed operation…10MHZ (typ.) at VDD=10V
  • •Standardized, symmetrical output characteristics
  • •100% tested for quiescent current at 20V
  • •5-V.10-V, and 15-V parametric ratings
  • •Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

 

CD4017 Applications

 

  • •Decade counter/decimal decode display(CD4017B)
  • •Binary counter/decoder
  • •Frequency division
  • •Counter control/timers
  • •Divide-by-N counting
  • •For further application information see ICAN-6166 “COS/MOS MSI Counter and Register Design and Applications”
Parametrics
Supply voltage Range VCC3-18V
Clock input Frequency fcl2.5-5.5MHZ
Clock Pulse Width,tW>60ns
Clock Inhibit Setup Time ts>70ns
Reset Pules Width tRW>60ns
Reset Removal Time,trem>150ns
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