HomedatasheetCD82C86H

CD82C86H Datasheet

CMOS Octal Bus Transceiver
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Description

Features, Applications

Description

The Intersil is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C86H provides a full eight-bit bi-directional bus interface a 20 lead package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C86H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation.

Features

Full Eight Bit Bi-Directional Bus Interface Industry Standard 8286 Compatible Pinout High Drive Capability - B Side IOL. - A Side IOL. 12mA Three-State Outputs Propagation Delay. 35ns Max. Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors Single 5V Power Supply Low Power Operation. ICCSB = 10�A Operating Temperature Range to +125oC

PART NUMBER 596287577012A 8MHz PACKAGE TEMP. RANGE to +85oC PKG. NO. N20.35 F20.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999

82C86H (PDIP, CERDIP) TOP VIEW 82C86H (PLCC, CLCC) TOP VIEW
= Logic One = Logic Zero = Input Mode = Output Mode = Don't Care = High Impedance PIN NAMES

DESCRIPTION Local Bus Data I/O Pins System Bus Data I/O Pins Transmit Control Input Active Low Output Enable

The transient current required to charge and discharge the 300pF load capacitance specified in the 82C86H/87H data sheet is determined by:

Assuming that all outputs change state at the same time and that dv/dt is constant;

During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal at or near the input switching threshold. Additionally, if the driving signal becomes high impedance ("float" condition), it could create an indeterminate logic state at the inputs and cause a disruption in device operation. The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower N-channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10�A during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices.

This current spike may cause a large negative voltage spike on VCC which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1�F ceramic disc capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible.


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