FDV302P product image


FAIRCHILD Semiconductor
This P-Channel logic level enhancement( FDV302P ) mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.
FDV302P Features
•-25 V, -0.12 A continuous, -0.5 A Peak.
- RDS(ON) = 13 W @ VGS= -2.7 V
- RDS(ON) = 10 W @ VGS = -4.5 V.
•Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V.
•Gate-Source Zener for ESD ruggedness. >6kV Human Body Model
•Compact industry standard SOT-23 surface mount package.
•Replace many PNP digital transistors (DTCx and DCDx) with one DMOS FET.


Drain-Source Breakdown Voltage:- 25 V
Gate-Source Breakdown Voltage:- 8 V
Continuous Drain Current:0.12 A
Resistance Drain-Source RDS (on):13 Ohms
Maximum Operating Temperature:+ 150 C
Fall Time:8 ns
Forward Transconductance gFS (Max / Min):0.135 S
Minimum Operating Temperature:- 55 C
Power Dissipation:0.35 W
Rise Time:8 ns
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