Methods for Evaluating Phase Noise Using a Distributed PLL System

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/ 2019-04-15 / News

For digital beamforming phased arrays, to generate a local oscillator (LO) , the usual implementation is to distribute it to the antenna array. A series of phase-locked loops assign common reference frequencies. For these distributed phase-locked loops, the method for evaluating the combined phase noise performance has not been fully documented in the literature.


In a distributed system, the common noise source is correlated, and if the distributed noise source is uncorrelated, it will decrease when the RF&#; This can be evaluated very intuitively for most components in the system. For a phase-locked loop, each component in the loop has a noise transfer function associated with it, and their contribution is a function of the control loop and any frequency translation. This adds complexity when trying to evaluate the combined phase noise output. Based on the known phase-locked loop modeling method and the evaluation of related and unrelated contributing factors, this paper proposes a method to track the contribution of distributed PLL under different frequency offsets.


For any radio system, it needs to be carefully designed for the receiver and exciter. Implementation. As digital beamforming continues to grow in phased array antenna systems, the distribution of LO signal and reference frequencies in a large number of distributed receivers and actuators complicates the design.


The factors that need to be weighed at the system architecture level include allocating the required LO frequency or assigning a lower frequency reference, and generating the required LO at a physical location near the point of use. Produced locally via a phase-locked loop LO  is a highly integrated, off-the-shelf option. The next challenge is to evaluate system-level phase noise from a variety of distributed components as well as centralized components.


The system using distributed phase-locked loop is shown in Figure 1. Common reference frequencies are assigned to multiple phase-locked loops, each producing an output frequency. The LO output in Figure 1a is assumed to be the LO input of the mixer of Figure 1b.


Figure 1. Distributed locks Phase loop system. Each oscillator is phase locked to a common reference oscillator. The LO signals from 1 to N are applied to the LO port of the mixer shown in the phased array.


One of the challenges faced by system designers is to track the noise contribution of distributed systems, understand related and uncorrelated noise sources, and estimate overall system noise. In a phase-locked loop, this challenge becomes more severe because the noise transfer function is a function of the frequency conversion and loop bandwidth settings in the phase-locked loop.


Motivation:Example of combined phase-locked loop measurement


Figure 2 shows an example of measurement for a combined phase-locked loop. These data were obtained by combining the transmit outputs from multiple  ADRV9009  transceivers. The figure shows the situation of a single  IC, two combinations IC and four combinations IC . For this data set, after the combination of  IC , you can see the obvious  10logN  improvements. To achieve this result, a low noise crystal oscillator reference source is required. The motivation for the next section of modeling is to derive a method for computing in large arrays with many distributed transceivers, and more broadly in any architecture with distributed phase-locked loops. How to change.



Figure 2. Phase noise measurement of two combined phase-locked loops.

Figure 2. Phase noise measurement of two combined phase-locked loops.


Phase Locked Loop Model


Noise in the phase-locked loop The model has been fully documented. 1-5 Fig. 3  shows the output phase noise map.In this type of diagram, the designer can quickly assess the noise contribution of each component in the loop, and these contributors add up to determine the overall noise performance. The model parameters are set to represent the data shown in Figure 2, and the source oscillator is used to estimate the phase noise when a large number of  IC 



Figure 3. A typical phase-locked loop phase noise analysis showing the noise contribution of all components. Total noise is the sum of all contributing factors.

Figure 3. A typical phase-locked loop phase noise analysis showing the noise contribution 

of all components.Total noise is the sum of all contributing factors.


To verify the effect of a distributed phase-locked loop, first derive the contribution of the reference contribution and the remaining PLL components from the PLL model.


Expanding a known PLL model to a distribution PLL model


This section describes the process of calculating combined phase noise for a system with multiple distributed phase-locked loops. The premise of this approach is to be able to separate the noise contribution of the reference oscillator from the noise contribution of the VCO and loop components. Figure 4 shows a hypothetical distributed example where one reference oscillator corresponds to multiple PLLs. This calculation assumes a noise-free distribution, which is impractical, but can be used to illustrate the principle. It is assumed that the noise contribution of the distributed PLL is irrelevant and is reduced by 10 logN, where N represents the number of distributed PLLs.As the channel increases, the noise is improved at larger offset frequencies, and for large distributed systems, the noise becomes almost entirely dominated by the reference oscillator.



Figure 4. Start with a distributed phase-locked loop phase noise modeling method: extract the phase noise contribution of the reference oscillator and all other components of the phase-locked loop except the reference oscillator from the phase-locked loop model. As a function of the number of distributed phase-locked loops, the combined phase noise assumes that the reference noise is correlated, while the noise contribution distributed between multiple PLLs is irrelevant.


The example shown in Figure 4 simplifies the assumption of the reference oscillator distribution. In true system analysis, system designers should also consider the noise contribution in the reference oscillator distribution, which will reduce overall results. However, simplified analysis like this is very useful,It can be seen how the trade-offs in the architecture can affect the overall phase noise performance of the system. Let's take a look at the effects of phase noise in distributed systems.


Description of phase noise in the reference distribution


This section evaluates two Examples of distribution options. The first case considered is shown in Figure 5. In this example, a wideband PLL that is commonly used to quickly tune the VCO frequency is selected. The distribution of the reference signal is achieved by the clock PLL IC, which is also often used to simplify the timing constraints of digital data links such as the JESD interface. The contribution factors are shown in the lower left corner.These contributing factors are at the frequency of the device and are not adjusted to the output frequency. The phase noise plot in the lower right corner shows the system level phase noise for a different number of distributed PLLs.


Figure 5.  Distributed wideband PLL with PLL IC in distribution.

Figure 5.  Distributed wideband PLL with PLL IC in distribution.


Some features of the model are worth noting. Assuming a high performance crystal oscillator with a nominal frequency of 100 MHz, the single contribution of the central oscillator is reflected in the higher end crystal oscillator available, although not necessarily the best and most expensive option available. Although the central oscillator output actually fan out to a limited number of distributed PLLs, these PLLs are again fanned out and repeated at a practical limit to achieve a complete distribution in the system. For the distribution contribution in this example, assume that there are 16 distribution components, and then assume that they will fan out again.The single contribution of the distribution circuit shown in the lower left corner is the noise of the PLL component without the reference oscillator contribution. The distribution in this example assumes the same frequency as the source oscillator and selects the noise contribution factor based on the typical IC available for this function.


The wideband PLL assumes an S-band nominal frequency and is set to use a 1 MHz loop bandwidth (as wide as possible with the actual loop bandwidth) for fast tuning.


It is worth noting that these models were chosen to represent possible realities and illustrate the cumulative effects in the array. Any detailed design may improve the specific PLL noise curve, which is expected, and this analysis is designed to help determine where the design resources should be allocated for optimal overall results, rather than engineering. In order to make a definitive statement relative to the available components.


The graph in the lower right corner of Figure 5 calculates the total combined phase noise of the LO distribution. The PLL noise transfer function, which uses various contributing factors, is applied to the output frequency and also includes the effect of the PLL loop bandwidth. The number of systems is also included, and assuming they are irrelevant, therefore,This contribution is reduced by 10 logN. Assuming a distribution number of 16, as previously mentioned, the distribution contribution is reduced by 10log16. In practice, this contribution will be further reduced as the distribution repeats. However, the additional noise contribution is not as significant. For fanout distribution in large arrays, the noise will be dominated by the first set of active devices. In the case of 16 groups of fan-outs, if each active device is an input to 16 other active devices, the additional distribution of 16 devices will only be reduced by ~0.25 when all devices are uncorrelated. ;dB. If this distribution continues, the overall contribution will be smaller. Therefore, in order to simplify the analysis, this effect is not considered, and the noise contribution of the distribution is obtained by calculating the first 16 parallel distribution components.


The resulting curve illustrates several effects. Similar to a single PLL model, the near-carrier noise is dominated by the reference frequency, the far-carrier noise is dominated by the VCO, and the far-carrier noise is improved when the uncorrelated VCOs are combined. This is quite intuitive. It is less intuitive that the value of the model accounts for a large proportion of the offset frequency dominated by the choice in the distribution.This result leads to a second example with a lower noise distribution and a narrower PLL loop bandwidth.


Figure 6 shows a different approach. The same low noise crystal oscillator is used as a reference. But it is distributed by the RF amplifier, not by PLL retiming and resynchronization. Choose a fixed frequency distributed PLL. This has two effects: when a single frequency is used and the tuning range is narrow, the VCO can be better in nature and the loop bandwidth can be made narrower. The graph in the lower left corner shows the various contributing factors. The central oscillator is the same as the previous example. Note the distributed amplifiers: When considering low phase noise amplifiers, their performance is not particularly high, but much better than using PLL LC (as in the previous example). When the VCO is better and the loop bandwidth is narrower, the distributed PLL will be improved at higher offset frequencies, but at the intermediate frequency of ~1 kHz, it is actually worse than the wideband PLL example. The lower right corner shows the combined result: the reference oscillator dominates the low frequency, and above the loop bandwidth, the performance is dominated by the distributed PLL and increases as the array size and number of distributed PLLs increases.


Figure 6 . Distributed narrowband PLL with amplifier in distribution.

Figure 6 . Distributed narrowband PLL with amplifier in distribution.


Figure 7 shows a comparison between the two examples. Note the wide range of differences in the ~2 kHz to 5 kHz offset frequency range.


Figure 7. Figure 5 and A comparison between Figure 6 shows a broad range of system-level performance based on the chosen distribution and architecture.


Distributed PLL Array Considerations

Based on a weighted contribution to overall system phase noise performance Understand that several conclusions can be drawn about the phased array or multichannel RF system architecture.


The traditional phase-locked loop design optimized for phase noise sets the loop bandwidth to the offset frequency to minimize the overall phase noise curve. The frequency at this time is generally the frequency at which the reference oscillator phase noise is normalized to the output frequency and intersects with the VCO phase noise. For having multiple phase-locked loops

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