How much advantage does VIO have over chipscope?

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/ 2019-07-19 / News

debug, especially the debug chip, there are many ways. A data frame from the entry to the output, can be set at the key nodes on the path, such as various counters, etc., can be reported to the real-time status through VIO (xilinx) timing. The VIO's various signal lines can be set to be similar to the structure of the CPU, and the monitor counter or status register can be programmed into the corresponding address, polling. Read back to the PC and capture data on the PC via TCL or other language. It is even possible to debug multiple FPGA chips through VIO, and the efficiency can be greatly improved by remote operation. In addition, you can also set up a special test frame, which can be used to make closed loops of various sizes, layer detection, and find problems.

How much advantage does this VIO have over chipscope?

The principle is the same,The difference is that it can be easily manipulated, you can write scripts to grab data, and you can control it remotely. VIO has inputs and outputs, and can be configured in real time. Http://xilinx.eetrend.com/blog/11987, VivadoVIO (virtual input output) virtual IO use;

I. Overview of usage

In general, VIO is used in the design to provide analog IO (we mainly use the function of analog output interface). As shown in Figure 1, the two output probe_out[0:0] and probe_out[7:0] of the vio_0 module in the red box can be directly used by other modules, but we do not need to use the actual interface on the board (such as button). So why do we pass the data to the inside of the FPGA with a click of the mouse on the computer? What is the data transferred to the inside of the FPGA? The answer is JTAG,The VIVADO software on the computer can communicate with the FPGA through the JTAG software. This is the principle that the VIO module emulates the IO pin inside the FPGA.

Figure 1 VIO IP core

1, configuration of VIO IP core

The following is a practical example to illustrate the configuration process of the VIO IP core:

In a design, need Use the button to start,However, there are no design buttons on the board, so you need to use VIO analog button input and other signal output. The specific process is as follows:

(1) instantiate the VIO IP core;

(2) Parameter configuration, configure the number of input probes and the number of output probes, as shown in Figure 2. You can set 0-256 each. (Generally, the input probe is not used. The most common one is the output probe, where both probes are shown in the figure).

Fig. 2 Probe number setting

(3) Configure output probe data bit width and initial value

Data bit width of the output probe, and initialization data (in hex) configuration as shown in Figure 3.

Figure 3 configuration Output probe data bit width and initial value

3, instantiation of VIO IP core

VIO IP core code is instantiated as shown below.

ILA_wrapper ILA(

.clk ( ),

.probe0 (),

.probe1 (),

.probe_out0 (),

.probe_out1 (),

.probe_in0 ()

);

4, use of VIO IP core

Add output probe on hw_vio interface, and Configure the corresponding parameters, at this time the output probe inside the FPGA will send a corresponding signal, as shown in Figure 4.

Figure 4 Use of VIO IP Core

Second, use VIO to achieve a large number of register read and write

1, background

in FPGA In debugging, if there is no CPU interface and operating system, but you also want to have a function similar to CPU and can read and write FPGA internal status register or configure FPGA internal register in real time, you can use VIO to implement an analog CPU interface. The following is a detailed introduction.

2, block diagram and VIO field definition

in Vivado 2016.2 software environment, Zedboard hardware platform, implements a sample project, the function of this project is that the computer runs Vivado software, and connects to zedboard through Jtag, uses VIO to simulate CPU interface, realizes register read and write function (the number of registers is 32) ,The number of bits is 32 bits), as shown in Figure 5.

Figure 5 block diagram

The parameter configuration description is as follows:

As shown in Figure 6, the first 32 bits of vio_out_1 are write addresses, and the last 32 bits are write data;

Figure 6 VIO write address and write data

As shown in Figure 7, vio_rd_addr represents the read address;

Figure 7 VIO read address

Figure 8 As shown,Vio_rd_data stands for read data

Figure 8 VIO read data

3, operation example

Here is an example of register reading and writing. Here, you don't need tcl scripts, you can use the Graphics interface directly, which is more convenient to use.

(1) Write data 32'hffff_ffff to the register with address 1, that is, configure vio_out_1[63:0] to be 64' h0000_0001_FFFF_FFFF,As shown in Figure 9.

Figure 9 VIO write data

(2) Set the read address to 1, observe the read data changes, as shown in Figure 10. .

Figure 10 VIO read data

Checking FIG. 10 shows that after the read address vio_rd_addr is 32' h0000_0001, the read data vio_rd_data[31:0] is changed from 32' h0000_0000 in FIG. 9 to 32'hffff_ffff in FIG. As with the written data, the register read and write operations are successful.

Three, source code

1, constraint file source

set_property PACKAGE_PIN Y9 [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports clk]

The above source code and constraint files apply to Xilinx's Zedboard development board In addition, the above is only a simple demonstration of the principle, you can apply the register to each of the internal key modules in your design, in the process of debugging, real-time data acquisition from the VIO interface, or dynamic configuration of the FPGA The internal registers are run in accordance with the functions of the register convention. Although there is no CPU, it is equivalent to the CPU, which can greatly improve the efficiency of FPGA debugging.VIO occupies resources similar to chipscope.

Keywords: Chip register
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