Homedatasheet018uStdCell

018uStdCell Datasheet

Standard Cell
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Features, Applications

Application

Flextronics Semiconductor's 0.18 � Standard Cell product suite offer designers the best optimization for performance, low power, and system cost. Applications benefiting from these features are telecom, networking, portable datacom, and consumer applications. The product suite is well equipped for design teams who intend to migrate from advanced FPGA to full system on chip ASIC as well as system architects who need to prototype with an ASIC. Production is "all about results" utilizing Flextronics manufacturing supply chain muscle to execute cycle-time and cost performance.

Description

Deep sub-micron CMOS silicon utilizing a 0.15� effective gate length capable to 250 MHz operation and 21M logic gates. Low power 1.8 volt core operation with 0.06 �W/gate/MHz power dissipation. Dense, fast SRAM, ROM, and Multi-port Register File compilers and instances. Low noise 3.3 v and 5.0 v tolerant I/O library designed for minimum die size / performance utilizing staggered, in-line, and flip-chip configurations. Complete pad sets tested for 4000 volts ESD and 300 ma latchup. Core Voltage I/O Voltage

Process 3.3 V operation 5.0 V tolerant Poly/Metal Density Power Dissipation gates/mm2) 0.06 �W/gate/MHz

Features Standard Cells I/O Functions Over 500+ cell engineered for optimum synthesis and high routability.

350+ CMOS/TTL functions with multiple drive strengths to 24 ma) 3.3 v and 5 v tolerant with built in level shifters. The 5 v tolerant function requires no external bias pin. PCI, SSTL, HSTL, USB, LVDS Clock driver, crystal oscillator, analog input, power, ground, and spacer cells for SoC compatibility. Single port SRAM compiler is a high density, high performance solution for embedded applications. Six transistor bordered bit cells achieve reduced die area while maintaining low tooling (mask) cost. The compilier maintains multi-bank architecture with capacity to 1 Mbit. High density dual port SRAM compiler offers a high performance solution with the highest density for embedded memory applications. Eight transistor bordered bit cells achieve minimum die area while maintaining low tooling (mask) cost. The compiler maintains multi-bank architecture with capacity to 1 Mbit. FSC18_012302

Features (continued) SRAM / 2P Register compiled high performance two port memory solution for embedded applications. Best solution for register files, buffer memories, fall-through FIFO, palette RAM, and tag RAM. Capacity to compile very wide words to 144 bits for address matching and virtual address. Low overhead of decode-logic and sense amplifiers minimize required die area. Read Only Memory compiler is a high density, fully diffused ROM solution targeted for embedded applications that require program store. The bit cells are optimized to offer very high density and low power. Configurations to 1 Mbit are available. Metal programmable versions are also available on a custom basis. Compiler based technology that allows system designers to choose the center frequency, duty cycle, and create a customized PLL. Fully modular and embedded in the I/O pad ring with no area overhead to the core � eliminates manual wiring of analog power supply or additional band-gaps / external components. Sophisticated frequency synthesizer targeted for applications such as pixel (dot clock) generation for use s a video master and non-integer clock multiplication for high-speed networking application. Cascaded PLL architecture for precision and phase jitter stability. Fully modular and embedded in the I/O pad ring with no area overhead to the core � eliminates manual wiring of analog power supply or additional band-gaps / external components.

Design Kit Support EDA views Verilog views with best case and worse case timing and power data VHDL views with best case and worse case timing and power data Synopsys views with best case and worse case timing and power data Data Books Typical timing & power data sheet for each cell Logic Data Book (typical case:25degrees C/1.8V) Inline I/O Cell Data Book (typical case:25degrees C/3.3V) Staggered I/O Cell Data Book (typical case:25degrees C/3.3V)

Our design kits include a broad selection of embedded semiconductor intellectual property components including standard cell logic, standard I/O, specialty I/O interfaces, memory, and PLL options. System on chip options include embedded RISC processors, buss standards, connectivity standards, high speed serial I/O, cryptology, and applied FEC applications. Please contact us regarding your specific requirements.

13/F. Hale Weal Industrial Bldg. 22-28 Tai Chung Road Tsuen Wan, Hong Kong Phone: 2276 1335 Fax: 2429 2768

Flextronics Semiconductor Inc. reserves the right to make changes in specifications at any time and without notice. The information furnished by Flextronics Semiconductor Inc. in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by Flextronics Semiconductor for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Flextronics Semiconductor Inc. This product is intended for use in normal commercial applications. Use of this product in applications such as life-support or life-sustaining equipment is specifically not authorized without the express written approval of the president of Flextronics Semiconductor, Inc.


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