035uGateArray Datasheet

Gate Array


Features, Applications


Flextronics Semiconductor's 0.35� family of gate arrays provides retargeting solutions for FPGA and Gate Array conversions. The Encore!Plus program is a retargeting service featuring direct replacement of FPGAs, PLDs, and ASICs, including other Gate Arrays, using Flextronics Semiconductor's 0.35� Gate Array technology. In most cases no new tools are required to take advantage of this service. Encore!Plus offers low-NRE, fastturnaround cycle times and flexible manufacturing. Flextronics Semiconductor's gate arrays use a sea-of-gates architecture with a novel gate design which allows high utilization while minimizing the effect of interconnect capacitance on circuit performance. Since gate arrays are personalized with the last few processing masks, a fast response time to customer orders can be made, allowing the customer more options in circuit definition. These gate arrays offer significant flexibility in pin definition. Contrary to designing with FPGAs, the customer can define any pin to be any signal function or power supply. The Encore!Plus program allows customers to redefine any pin's electrical parameters. Customers may select their choice of pin characteristics, such as output drive levels, slew rate control, different input switching points and hysteresis. All prototypes are not only fully tested prior to shipment, but are assembled in the production package on the production line. This allows the customer to use prototypes as if they were production parts.


Five array sizes: to 2M gates to 680 pads 3.3 volt operation Flexible pin assignments Conversion from FPGAs, PLDs, and ASICs, (including other gate arrays) Low power dissipation High gate utilization Sea-of-Gates architecture Functional logic equivalent guaranteed

0.35� Gate Arrays Flextronics Semiconductor's 0.35� Gate Array Family

The 0.35� gate array family currently consists of five arrays, and new arrays can be added as the need arises. Table 1 provides examples of the current arrays, their size and the number of pins. These gate arrays have been designed with a maximum number of power and I/O pads. This allows Flextronics Semiconductor to offer the most cost-effective array size, especially in those cases where the design is limited by the number of I/O connections, rather than by the number of gates. can be added, and there is also an optional pull-up or pull-down resistor. Outputs vary by strength. Output strengths from 24 mA may be specified individually for each pin. Higher currents may be obtained by paralleling I/O pads. The control logic for the outputs allows an output to be continuous, tristate or open-drain. Slew rate control is added on all outputs whose strength is in excess of 8 mA. Flextronics Semiconductor's gate array family also supports open-drain outputs with a dynamic precharge for extra system speed. Any output may be combined with any input to create a bi-directional I/O buffer with a choice of characteristics.

Flextronics Semiconductor's gate arrays have been designed to act as a replacement for many existing gate arrays and FPGAs. This means that the internal power busses are designed to be strong enough to support other vendors' rules on the number of supply pins necessary to support a given number and strength of outputs. For new designs, the number of power pins required is a trade-off between the number of pins available and the ability of the PC board to provide a clean, lowinductance supply. Flextronics Semiconductor can skew simultaneous switching outputs upon request. We also add slew rate controls to all high-power outputs to minimize the peak currents associated with output switching. Flextronics Semiconductor recommends replacing some or all no-connect pins with supply pins, as a means of increasing the amount of margin within the design.

Flextronics Semiconductor's gate arrays have been designed so that any pin may be assigned any input/ output (I/O) function, including power and ground. This flexibility allows gate arrays to match any existing pinout, creating an exact replacement for either FPGAs, PLDs, or ASICs, (including gate arrays). The internal power supply busses are designed to prevent any output switching transients from affecting the internal logic.

The gate array family I/O buffers are designed so that only the guard-banded, output drive transistors and the pull-up /pull-down transistors are dedicated to a specific pin. All of the output control logic and the input level translators are built from internal array transistors. Since these internal transistors are not dedicated to a specific buffer, a number of different I/O functions may be created. Input buffers may be designed to work with either CMOS or TTL levels. In either case, a Schmitt trigger

Flextronics Semiconductor's gate arrays are made up of uncommitted transistors, and there are no arbitrary limits as to how these transistors may be used. We will create specific functions upon request. Flextronics Semiconductor can provide circuitry to support PCI, JTAG, crystal oscillators, RC oscillators, current mirrors, etc. and the libraries include a variety of synthesizable cores.

For netlist conversions, Flextronics Semiconductor supports multiple formats and industry-standard tools. To convert a customer's design, Flextronics Semiconductor needs a netlist of the circuit, vectors and a pinout. Additional information, such as the timing of a critical path, may be supplied if such a path needs additional evaluation. information to Flextronics Semiconductor engineering about the expected device performance. Table 2 shows a Print-on-Change format for an exclusive-OR (XOR) gate.

A netlist defines the logic to be implemented in the gate array. While most gate-level formats are acceptable to the Encore!Plus program, the netlist must be in ASCII format. Most binary netlists are proprietary and undocumented, which prevents Flextronics Semiconductor from translating them. Examples of acceptable netlist formats include: XNF EDIF ADL LDL TDL QDF Wire File (Xilinx) (Altera, others) (Actel) (LSI Logic) (Toshiba) (QuickLogic) (ViewLogic)

Flextronics Semiconductor requires a listing of pin numbers, pin names and the function and/or specifications for the input and output pins. This list should include any special characteristics that the pin must have, such as TTL-level input or open-drain output. The pin list also provides customers with a means to modify the I/O characteristics normally associated with FPGA netlists. The default is to use the I/Os specified by the original FPGA manufacturer. By referencing different specifications in the pin file, the customer can obtain any desired I/O characteristics. Table 3 lists some typical pinout specifications

Flextronics Semiconductor prefers simulations at 1 MHz are supplied by the customer. In the event that simulations are not available, assistance in the development of simulation vectors can be provided. Flextronics Semiconductor provides a service to enhance test vectors using methods such as ATPG and SCAN. Flextronics Semiconductor uses the customer's vectors to confirm that the design has been correctly converted into the Flextronics Semiconductor format, and to develop the production test vectors. Using low-speed simulations makes it easier to verify the functionality of the logic. High-speed simulations, particularly with FPGAs, often produce vectors with signals which take more than one clock cycle to propagate to the output. Such vectors make it difficult to verify a correct design conversion. Flextronics Semiconductor will evaluate and confirm higher speed simulations upon request. The preferred format for simulations is to show every signal pin in a table, with the simulation output in a "Print-On-Change" format. This supplies significant

Input - TTL Input - TTL Input - TTL Input - CMOS w/10K pull-up resistor Input - CMOS w/10K pull-up resistor Supply Bidirectional 12 mA Supply Input - TTL Bidirectional mA No Connect Supply Input - TTL Output 6 mA Output 6 mA Supply



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