Flextronics Semiconductor's 0.35� Standard Cell product suite offers designers the best optimization for 3.3 voltage performance and power. Applications benefiting from these features are telecom, networking, portable datacom, and consumer applications. The product suite is well equipped for design teams who intend to migrate from advanced FPGA to full system on chip ASIC as well as system architects who need to prototype with an ASIC. Production is "all about results" utilizing Flextronics manufacturing supply chain muscle to execute cycle-time and cost performance.Description
Sub-micron CMOS silicon utilizing a 0.32� effective gate length capable to 125 MHz operation and 4.5 M logic gates. Low power 3.3 volt core operation with 0.2 �W/gate/MHz power dissipation. Dense, fast SRAM memory compilers and instances. Low noise 3.3V and 3.3V with 5.0V tolerant I/O library designed for minimum die size / performance utilizing staggered and in-line configurations. Complete pad sets tested for 2 kV (HBM) ESD and 100 mA latchup. Poly/Metal Density Power Dissipation Core Voltage I/O Voltage Process 3.3 V operation 5.0 V tolerant gates/mm2) 0.2 �W/gate/MHzStandard Cell I/O Functions Application Specific I/O SRAM / 1P
Over 450 cells engineered for optimum synthesis and high routability. 300+ CMOS/TTL functions with multiple drive strengths to 24 mA) 3.3V and to 6 mA) 5V tolerant. The 5V tolerant function requires no external bias pin. PCI, PECL, GTL, USB, LVDS, POR Clock driver; crystal oscillator; analog input; power, ground, & spacer cells for SoC compatibility. Single port SRAM compiler is a high density, high performance solution for embedded applications. Six transistor bordered bit cells achieve reduced die area while maintaining low tooling (mask) cost. The compilier maintains multi-bank architecture with capacity to 576 Kbits. High density dual port SRAM compiler offers a high performance solution with the highest density for embedded memory applications. Eight transistor bordered bit cells achieve minimum die area while maintaining low tooling (mask) cost. The compiler maintains multi-bank architecture with capacity to 576 Kbits. Programmable PLL with external divider allows designers to create a customized PLL for clock management in the system design. Sophisticated frequency synthesizer targeted for applications such as pixel (dot clock) generation for use as a video master and non-integer clock multiplication for high-speed networking application. Cascaded PLL architecture for precision & phase jitter stability. FSC35_012402
EDA views Verilog views with best case and worse case timing and typical case power data VHDL views with best case and worse case timing and typical case power data Synopsys views with best case and worse case timing and typical case power data Our design kits include a broad selection of embedded semiconductor intellectual property components including standard cell logic, standard I/O, specialty I/O interfaces, memory, and PLL options. System on chip options include bus standards, connectivity standards, high speed serial I/O, cryptology, and applied FEC applications. Please contact us regarding your specific requirements. NORTH AMERICA 169 West Java Drive Sunnyvale, CA 94089 Phone: 744 1800 Fax: Revere Dr #200 Northbrook, IL 60062 Phone: (847) 509-5870 Fax: 509-5872 100 Cummings Ctr., Suite 323A Beverly, MA 01915 Phone: 921 0131 Fax: Oak Ridge Turnpike Oak Ridge, TN 37830 Phone: 482 4616 Fax: 482 8939 ASIA-PACIFIC 13/F. Hale Weal Industrial Bldg. 22-28 Tai Chung Road Tsuen Wan, Hong Kong Phone: 2276 1335 Fax: 2429 2768 EUROPE 3-5 North Street Leatherhead, Surrey KT22 7AX England Phone: Fax: Lev-Pesach St. Ofek 1 Bldg. North Industrial Park Lod 71293 Israel Phone: Fax: Postbus 5520 AC Eersel The Netherlands Phone: Fax: Fabrikorvagen 8, Box SE-131 27 Nacka Strand Sweden Phone: Fax:
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