|100329 Low Power Octal ECL/TTL Bidirectional Translator with Register
The is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is -2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus. The 100329 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 k pull-down resistors.Features
s Bidirectional translation s ECL high impedance outputs s Registered outputs s FAST TTL outputs s 3-STATE outputs s Voltage compensated operating range -5.7V s High drive IOS
Order Number 100329QC 100329QI Package Number N24E V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range to +85�C)
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.FAST is a registered trademark of Fairchild Semiconductor Corporation.
Pin Names OE CP DIR TTL Data I/O Output Enable Input Clock Pulse Input (Active Rising Edge) Direction Control Input Description ECL Data I/O
OE DIR CP X ECL Port Input LOW (Cut-Off) H X (Note 1) (Note 1) (Note 1)(Note 3) (Note 2) (Note 2) (Note 2)(Note 3)
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Clock Transition = No Change
Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP.
Storage Temperature (TSTG) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 6) TTL Input Current (Note 6) Voltage Applied to Output in HIGH State 3-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 5) twice the rated IOL (mA)Case Temperature (TC) ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) to +85�C
Note 4: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: ESD testing conforms to MIL-STD-883, Method 3015. Note 6: Either voltage limit or current limit is sufficient to protect inputs.
VEE to -5.7V, VCC = VCCA = GND, to +85�C, VTTL to +5.5V (Note 7) Symbol Parameter Min Typ Max Units VOH VOL Output HIGH Voltage Output LOW Voltage Cutoff Voltage -2000 VOHC VOLC VIH VIL IIH IIL VFCD IEE Output HIGH Voltage Corner Point HIGH Output LOW Voltage Corner Point LOW Input HIGH Voltage Input LOW Voltage Input HIGH Current Breakdown Test Input LOW Current Input Clamp Diode Voltage VEE Supply Current mA mV VIN = VIH (Min) or VIL (Max) �A V Loading with to -2V Over VTTL, V EE, TC Range Over VTTL, V EE, TC Range VIN = +2.7V VIN = +5.5V VIN = +0.5V IIN mA LE LOW, OE and DIR HIGH Inputs Open VEE to -4.8V VEE -5.7V mV Conditions VIN = VIH (Max) or VIL (Min) Loading with OE or DIR LOW, VIN = VIH (Max) or VIL (Min) Loading with -2V -1035
Note 7: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.