Homedatasheet16C2852

16C2852 Datasheet

Dual Uart With TX And RX Fifo Counters
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Description

Features, Applications
DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX DIRECTION CONTROL
DESCRIPTION

The is a dual universal asynchronous receiver and transmitter (UART). The device is designed for high performance communication systems to provide maximum full-duplex data throughput. Each UART provides enhanced functions with 128 byte of transmit and receive FIFOs, automatic RTS/CTS and software flow control, programmable FIFO trigger level, automatic RS-485 half duplex transmit/receive direction control, wireless infrared (IrDA ver 1.0) data encoder/decoder, and a modem control interface. Onboard status registers provide the user with error indications and operational status. An alternate function register supports concurrent write to UART A and B. System interrupts and modem control features may be tailored by software to meet user requirements. Independent programmable baud rate generators are provided to select data rates to 1.5 Mbps. An internal loopback capability allows onboard diagnostics. The 2852 is available a 44-pin PLCC package and is pin-to-pin and functionally compatible with the ST16C2552. The device is fabricated in advanced CMOS process to achieve low power and high speed requirements.

FEATURES

Pin and functionally compatible to ST16C2552, and National PC16552/NS16C552 Independent channel A/B control to 1.5 Mbps data rate operation 128 byte transmit FIFO to reduce CPU bandwidth requirement 128 byte receive FIFO with error flags to reduce CPU bandwdth requirement Programmable transmit and receive FIFO trigger level from to 127 Automatic RTS/CTS flow control with hysteresis Automatic software flow control Automatic RS485 half duplex direction control on -RTS pin. Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break) Infrared (IrDA ver 1.0) transmit and receive data encoder/decoder Device identification and revision Standard 460.8 Kbps transmit/receive data rate with 7.3728 MHz crystal or external clock source or 3.3V operation Industrial and commercial temperature grades 44-pin PLCC package

RXA TXA -DTRA -RTSA -MFA INTA VCC -TXRDYB -RIB -CDB -DSRB
Part number Pins Package Operating temperature
Flow Control Logic Receive FIFO Registers

Address-0 Select Bit. - Internal register address selection. Address-1 Select Bit. - Internal register address selection. Address-2 Select Bit. - Internal register address selection. Channel Select - UART channel B is selected by the logical state of this pin when the -CS is a logic 0. A logic 0 on CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A4. Chip Select (active low) - This function selects channel B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the Bit-0 of the Alternate Function Register (AFR) can temporary override CHSEL function, allowing the user to write to both channel registers simultaneously with one write cycle. It is specially useful in the initialization routine. Data Bus (Bi-directional, tri-state) - These pins are the eight bit, three state data bus for transferring information to or from the controlling external CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Interrupt A-B (active high) - This function is associated with individual channel interrupts, INT A-B. Interrupts are enabled in the interrupt enable register (IER), and becomes a logic 1 whenever an interrupt condition exists. Interrupt conditions include: receive data buffer ready, receive data time-out, receive errors, transmit buffer empty, or when a modem status change is detected. Read strobe (active low - A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the data bus (D0-D7) for access by user CPU. Write strobe (active low) - A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2. Multi-Function A-B - This function is associated with an individual channel function, or B. User programmable bits 1-2 of the Alternate Function


Features

Parameters

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Manufacturer information

EXAR CORPORATION

Exar Corporation delivers highly differentiated silicon, software and subsystem solutions for industrial, datacom and storage applications. For nearly 40 years, Exar's comprehensive knowledge of end-user markets along with the underlying analog, mixed signal and digital technology has enabled innovative solutions that meet the needs of the evolving connected world. Exar's product portfolio includes power management and interface components, communications products, storage optimization solutions, network security and applied service processors. Exar has locations worldwide providing real-time customer support to drive rapid product development. For more information about Exar

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