2032E Datasheet

ispLSI 2000E Family


Features, Applications
In-System Programmable SuperFASTTM High Density PLD Features

SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 225 MHz Maximum Operating Frequency tpd 3.5 ns Propagation Delay TTL Compatible Inputs and Outputs 5V Programmable Logic Core ispJTAGTM In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port User-Selectable or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems PCI Compatible Outputs (48-Pin Package Only) Open-Drain Output Option Electrically Erasable and Reprogrammable Non-Volatile Unused Product Term Shutdown Saves Power ispLSI OFFERS THE FOLLOWING ADDED FEATURES Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERTTM � LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM PC and UNIX Platforms


The ispLSI is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032E device is the Generic Logic Block (GLB). The GLBs are labeled A1.. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually

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programmed be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common or 3.3V power supply, I/O output levels can be matched or 3.3V compatible voltages. When connected a 5V supply, the I/O pins provide PCI-compatible output drive (48-pin device only). Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032E device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.

Clocks in the ispLSI 2032E device are selected using the dedicated clock pins. Three dedicated clock pins or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.

In addition to the standard output configuration, the outputs of the ispLSI 2032E are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.

Supply Voltage Vcc.................................. to +7.0V Input Voltage Applied........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied..... -2.5 to VCC +1.0V Storage Temperature................................ to 150�C Case Temp. with Power Applied.............. to 125�C Max. Junction Temp. (TJ) with Power Applied... 150�C

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

SYMBOL PARAMETER Supply Voltage: Logic Core, Input Buffers Supply Voltage: Output Drivers Input Low Voltage Input High Voltage to +70�C MIN. MAX. Vcc+1 UNITS

SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock Capacitance TYP 7 10 UNITS pf TEST CONDITIONS VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VI/O = 2.0V VCC = 2.0V

PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM � UNITS Cycles



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