Homedatasheet203A665

203A665 Datasheet

128K X 8 Radiation Hardened Static RAM 3.3 V
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Features

Other Read/Write Cycle Times 30 ns, to 125 �C) SMD Number 5962H98615 Asynchronous Operation CMOS Compatible I/O Single V �5% Power Supply Low Operating Power Packaging Options 40-Lead Flat Pack x 0.650")

Radiation Fabricated with Bulk CMOS 0.5 �m Process Total Dose Hardness through 1x106 rad(Si) Neutron Hardness through 1x1014 N/cm2 Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s Soft Error Rate < 1x10-11 Upsets/Bit-Day Dose Rate Survivability through 1x1012 rad(Si)/s Latchup Free

The x 8 radiation hardened static RAM is a high performance 131,072 word x 8-bit static random access memory with industrystandard functionality. It is fabricated with BAE SYSTEMS' radiation hardened technology and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires a single V �5% power supply. The RAM is available with CMOS compatible I/O. Power consumption is typically less than 20 mW/MHz in operation, and less than mW in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 30 nanoseconds. BAE SYSTEMS' enhanced bulk CMOS technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques.

� Address input pins that select a particular eight-bit word within the memory array. � Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. � Negative chip select, when at a low level, allows normal read or write operation. When at a high level, S forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables the data input buffers only. If this signal is not used, it must be connected to GND.

� Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at a high level, W allows normal read operation. � Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined S, W, and E. If this signal is not used it must be connected to GND. � Chip enable, when at a high level allows normal operation. When at a low level, E forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the S input buffer. If this signal is not used, it must be connected to VDD.

1) VIN for don't care (X) inputs = VIL or VIH. Active Standby 2) When G = high, I/O is high-Z. 3) To dissipate the minimum amount of standby power when in standby mode: S= VDD and E = GND. All other input levels may float.

Storage Temperature Range (Ambient) Operating Temperature Range Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4)

1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015.

Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" - CMOS Input Logic "High" - CMOS

The substrate of this module is connected directly to Ground. Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: Power-Up Sequence: GND, VDD, Inputs Power-Down Sequence: Inputs, VDD, GND


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