Homedatasheet21150AA

21150AA Datasheet

Pci-to-pci Bridge
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Description

Features, Applications

Complies fully with the PCI Local Bus Specification, Revision 2.1 Complies fully with the Advanced Configuration Power Interface (ACPI) Specification Complies fully with the PCI Power Management Specification, Revision 1.01 Complies fully with Revision 1.0 of the PCI-to-PCI Bridge Architecture Specification Implements delayed transactions for all PCI configuration, I/O, and memory read commands--up to three transactions simultaneously in each direction Allows 88 bytes of buffering (data and address) for posted memory write commands in each direction--up to five posted write transactions simultaneously in each direction Allows 72 bytes of read data buffering in each direction Provides concurrent primary and secondary bus operation, to isolate traffic Provides 10 secondary clock outputs with the following features: Low skew permits direct drive of option slots Individual clock disables, capable of automatic configuration during reset Provides arbitration support for nine secondary bus devices: A programmable 2-level arbiter Hardware disable control, to permit use of an external arbiter

Provides a 4-pin general-purpose I/O interface, accessible through devicespecific configuration space Provides enhanced address decoding: A 32-bit I/O address range A 32-bit memory-mapped I/O address range A 64-bit prefetchable memory address range ISA-aware mode for legacy support in the first 64KB of I/O address range VGA addressing and VGA palette snooping support Includes live insertion support Supports PCI transaction forwarding for the following commands: All I/O and memory commands Type 1 to Type 1 configuration commands Type 1 to Type 0 configuration commands (downstream only) All Type 1 to special cycle configuration commands Includes downstream lock support Supports both 5-V and 3.3-V signaling environments Available in both 33 MHz and 66 MHz versions Provides an IEEE standard 1149.1 JTAG interface.

For 21150-AB and later revisions only. The 21150-AA does not implement this feature.

Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 21150 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at http://www.intel.com. Copyright � Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.

1.0 Introduction......................................................................................................................... Architecture........................................................................................................... 3 Data Path.............................................................................................................. 5 Posted Write Queue.............................................................................................. 6 Delayed Transaction Queue.................................................................................. 6 Read Data Queue................................................................................................. 6

Signal Pins......................................................................................................................... Primary PCI Bus Interface Signals........................................................................ 8 Secondary PCI Bus Interface Signals.................................................................11 Secondary Bus Arbitration Signals......................................................................13 General-Purpose I/O Interface Signals...............................................................14 Clock Signals.......................................................................................................14 Reset Signals......................................................................................................15 Miscellaneous Signals.........................................................................................16 JTAG Signals......................................................................................................17

PCI Bus 4.1 4.2 Types of Transactions.........................................................................................27 Address Phase....................................................................................................28 4.2.1 Single Address Phase............................................................................28 4.2.2 Dual Address Phase...............................................................................28 Device Select (DEVSEL#) Generation................................................................29 Data Phase..........................................................................................................29 Write Transactions..............................................................................................29 4.5.1 Posted Write Transactions.....................................................................30 4.5.2 Memory Write and Invalidate Transactions............................................32 4.5.3 Delayed Write Transactions...................................................................32 4.5.4 Write Transaction Address Boundaries..................................................34 4.5.5 Buffering Multiple Write Transactions.....................................................35 4.5.6 Fast Back-to-Back Write Transactions...................................................35 Read Transactions..............................................................................................36 4.6.1 Prefetchable Read Transactions............................................................37 4.6.2 Nonprefetchable Read Transactions......................................................37 4.6.3 Read Prefetch Address Boundaries.......................................................38 4.6.4 Delayed Read Requests........................................................................38 4.6.5 Delayed Read Completion with Target...................................................39 4.6.6 Delayed Read Completion on Initiator Bus............................................39 Configuration Transactions.................................................................................42 4.7.1 Type 0 Access to the 21150...................................................................43 4.7.2 Type 1 to Type Translation..................................................................44 4.7.3 Type 1 to Type Forwarding.................................................................45 4.7.4 Special Cycles........................................................................................46


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