Phase-Lock Loop Clock Distribution for Applications ranging from to 133MHz operating frequency Distributes one clock input to two banks of four outputs Separate output enable for each output bank External feedback (FBK) pin is used to synchronize the outputs to the clock input Output Skew <200 ps Low jitter <200 ps cycle-to-cycle 2x, 4x output options (see table): IDT2308-1H, -2H, and -5H for High Drive No external RC network required Operates at 3.3V VDD Available in SOIC and TSSOP packages
The is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range to 133MHz. The IDT2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25�A. The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT2308 is characterized for both Industrial and Commercial operation.The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Symbol VDD Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) IIK (VI < 0) IOK (VO VO > VDD) IO (VO 0 to VDD) VDD or GND = 55�C (in still air)(3) TSTG Operating Storage Temperature Range Commercial Temperature Range Industrial Temperature Range +70 �C Continuous Current Maximum Power Dissipation mA W Input Clamp Current Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) Continuous Output Current �50 mA Max. �50 mA Unit (2) VI
Functional Description Input Reference Clock, 5 Volt Tolerant Input Clock Output for Bank A Clock Output for Bank A 3.3V Supply Ground Clock Output for Bank B Clock Output for Bank B Select Input, Bit 2 Select Input, Bit 1 Clock Output for Bank B Clock Output for Bank B Ground 3.3V Supply Clock Output for Bank A Clock Output for Bank A PLL Feedback Input
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150�C and a board trace length of 750 mils.SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs
NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs.
NOTE: H = HIGH Voltage Level L = LOW Voltage Level
Device IDT2308-4 IDT2308-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference 2 x Reference 2 x Reference 2 x Reference 4 x Reference 2 x Reference Reference/2 Bank B Frequency Reference Reference/2 Reference Reference/2 Reference 2 x Reference 2 x Reference Reference/2NOTE: 1. Output phase is indeterminant or 180� from input clock).