Homedatasheet24AA64

24AA64 Datasheet

I2C->64K to 512K
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Description

Features, Applications

Part Number 24AA64 24LC64 VCC Range 1.8-5.5 2.5-5.5 Max Clock Frequency kHz(1) 400 kHz Temp Ranges I, E

Description

The Microchip Technology Inc. a 64 Kbit Electrically Erasable PROM. The device is organized as eight blocks x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 1.8V with standby and active currents of only 1 �A and 1 mA respectively. It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24XX64 also has a page-write capability for to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for to 512 Kbits address space. The 24XX64 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP and MSOP packages.

Features

Single supply with operation down to 1.8V Low power CMOS technology 1 mA active current typical 1 �A standby current (max.) (I-temp) Organized as 8 blocks of 8K bit (64K bit) 2-wire serial interface bus, I2CTM compatible Cascadable for up to eight devices Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz (24AA64) and 400 kHz (24LC64) compatibility Self-timed write cycle (including auto-erase) Page-write buffer for to 32 bytes 2 ms typical write cycle time for page-write Hardware write protect for entire memory Can be operated as a serial ROM Factory programming (QTP) available ESD protection 4,000V 1,000,000 erase/write cycles Data retention > 200 years 8-lead PDIP, SOIC, TSSOP, and MSOP package Available temperature ranges: - Industrial (I): +85�C - Automotive (E): to +125�C

*24XX64 is used in this document as a generic part number for the 24AA64/24LC64 devices.

VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS......................................................................................................... -0.3V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C ESD protection on all pins...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

VCC to +5.5V Industrial (I): TAMB to +85�C Automotive (E): TAMB to +125�C Min

Characteristic WP, SCL and SDA pins High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs)

(Note 1) IOL = 3.0 mA, VCC = 2.5V VIN =.1V to VCC VOUT =.1V to VCC = 5.0V (Note 1) TAMB = 25�C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz Industrial Automotive SDA = SCL = VCC WP = VSS

Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical measurements taken at room temperature.

VCC to +5.5V Industrial (I): TAMB to +85�C Automotive (E): TAMB to +125�C Characteristic Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time Min Max Units kHz ns Conditions 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC 2.5V (24AA64) (Note 1) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC 2.5V (24AA64) (Note 2) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC (24AA64) 2.5V VCC 5.5V 1.8V VCC 2.5V (24AA64) (Notes 1 and 3)

THD:STA START condition hold time TSU:STA START condition setup time

THD:DAT Data input hold time TSU:DAT Data input setup time TSU:STO STOP condition setup time TAA TBUF Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start

Output fall time from VIH min- 20+0.1CB imum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance 1M

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's website: www.microchip.com.


Features

Parameters

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