Homedatasheet24C01B

24C01B Datasheet

Note:this Product Has Become 'Obsolete' And is no Longer Offered as a Viable Device For Design
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Description

Features, Applications
FEATURES

Single supply with 5.0V operation Low power CMOS technology 1 mA active current typical 10 �A standby current typical 5 �A standby current typical at 5.0V Organized as a single block of 128 bytes or 256 bytes 8) 2-wire serial interface bus, I2C compatible 100 kHz compatibility Self-timed write cycle (including auto-erase) Page-write buffer for to 8 bytes 2 ms typical write cycle time for page-write Hardware write protect for entire memory Can be operated as a serial ROM ESD protection 3,000V 1,000,000 ERASE/WRITE cycles guaranteed Data retention > 200 years 8 pin DIP or SOIC package Available for extended temperature ranges - Automotive (E): to +125�C

DESCRIPTION

The Microchip Technology Inc. 24C01B and 24C02B are 1K bit and 2K bit Electrically Erasable PROMs. The devices are organized as a single block x 8 bit x 8 bit memory with a 2-wire serial interface. The 24C01B and 24C02B also have page-write capability for to 8 bytes of data. The 24C01B and 24C02B are available in the standard 8-pin DIP and an 8-pin surface mount SOIC package. These devices are for extended temperature applications only. It is recommended that all other applications use Microchip's 24LC01B/02B.

Function Ground Serial Address/Data I/O Serial Clock Write Protect Input +5.0V Power Supply No Internal Connection

VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS................-0.6V to VCC +1.0V Storage temperature..................................... to +150�C Ambient temp. with power applied................. to +125�C Soldering temperature of leads (10 seconds)............. +300�C ESD protection on all pins............................................. 4 kV

*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

VCC to 5.5V Automotive (E): Tamb to 125�C Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS -10 --.05 VCC Min.7 VCC.3 VCC Max. Units �A �mA mA �A VCC = 3.0V, SDA = SCL = VCC = 5.5V, SDA = SCL = VCC (Note) IOL = 3.0 mA, VCC = 2.5V VIN to 5.5V VOUT to 5.5V VCC = 5.0V (Note 1) Tamb = 25�C, FCLK = 1 MHz VCC = 5.5V, SCL = 100 kHz Conditions

All parameters apply across the specified operating ranges unless otherwise noted. Parameter WP, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmidt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note:

Vcc to 5.5V Automotive (E): Tamb to +125�C, All Parameters apply across the specified operating ranges unless otherwise noted

Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance

Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF TOF TSP TWR

After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)

Time the bus must be free before a new transmission can start (Note 100 pF (Note 3) Byte or Page mode 25�C, Vcc = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL TSU:STA SDA IN THD:STA TSP TAA SDA OUT THD:STA THD:DAT TSU:DAT TSU:STO

Features

Parameters

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