24C01SC Datasheet

I2C->128 to 1K


Features, Applications

ISO Standard 7816 pad locations Low power CMOS technology 1 mA active current typical 10 �A standby current typical at 5.5V Organized as a single block of 128 bytes or 256 bytes 8) 2-wire serial interface bus, I2CTM compatible 100 kHz and 400 kHz compatibility Self-timed write cycle (including auto-erase) Page-write buffer for to 8 bytes 2 ms typical write cycle time for page-write ESD protection > 4 kV 1,000,000 E/W cycles guaranteed Data retention > 200 years Available for extended temperature ranges - Commercial (C): to +70�C


The Microchip Technology Inc. 24C01SC and 24C02SC are 1K-bit and 2K-bit Electrically Erasable PROMs with bondpad positions optimized for smart card applications. The devices are organized as a single block x 8-bit memory with a two-wire serial interface. The 24C01SC and 24C02SC also have page-write capability for to 8 bytes of data.

Function Ground Serial Address/Data I/O Serial Clock to 5.5V Power Supply Don't connect

VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS............... -0.6V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C ESD protection on all pads............................................ S4 kV

*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

VCC to +5.5V Parameter Symbol Min. Commercial (C): Tamb = Max. Units to +70�C Conditions

SCL and SDA pads: High level input voltage Low level input voltage Hysteresis of Schmidt trigger inputs Low level output voltage Input leakage current (SCL) Output leakage current (SDA) Pin capacitance (all inputs/outputs)

.7 VCC VIH VIL --.3 VCC VHYS.05 VCC VOL --.40 ILI -10 10 ILO -10 10 CIN, 10 COUT Operating current ICC Write 3 ICC Read 1 Standby current ICCS 100 Note: This parameter is periodically sampled and not 100% tested.

Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Min. Max. Units kHz ns Remarks

(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)

Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance

(Note 2) Time the bus must be free before a new transmission can start (Note 100 pF (Note 3) Byte or Page mode 25�C, Vcc = 5V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.




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