Single supply with operation from to 5.5V Low power CMOS technology 1 mA active current typical 10 �A standby current typical at 5.5V Organized as a single block of 256 bytes x 8) Hardware write protection for upper half of array 2-wire serial interface bus, I2C compatible 100 kHz and 400 kHz compatibility Page-write buffer for to 16 bytes Self-timed write cycle (including auto-erase) Fast 1 mS write cycle time for byte or page mode Address lines allow up to eight devices on bus 1,000,000 erase/write cycles guaranteed ESD protection > 4,000V Data retention > 200 years 8-pin PDIP, SOIC or TSSOP packages Available for extended temperature ranges - Commercial (C): +70�C - Industrial (I): +85�C - Automotive (E): to +125�CDESCRIPTION
The Microchip Technology Inc. a 2K bit Serial Electrically Erasable PROM with a voltage range to 5.5V. The device is organized as a single block x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 10 �A and 1 mA respectively. The device has a page-write capability for to 16 bytes of data and has fast write cycle times of only 1 mS for both byte and page writes. Functional address lines allow the connection up to eight 24C02C devices on the same bus for to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and TSSOP packages.SDA SCL Vcc Vss Write Protect Circuitry YDEC SENSE AMP R/W CONTROL
Function Ground Serial Data Serial Clock to 5.5V Power Supply Chip Selects Hardware Write Protect
VCC........................................................................7.0V All inputs and outputs w.r.t. VSS.....-0.6V to VCC +1.0V Storage temperature.......................... to +150�C Ambient temp. with power to +125�C Soldering temperature of leads (10 seconds).. +300�C ESD protection on all pins..................................... 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VCC to +5.5V Commercial (C): Industrial (I): Automotive (E): Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Read ICC Write ICCS Min. 0.7 VCC 0.05 VCC -10 Tamb to +70�C Tamb to +85�C Tamb to +125�C Max. 0.3 VCC Units mA �A (Note) IOL = 3.0 mA, Vcc = 4.5V VIN WP = Vss VOUT to 5.5V VCC = 5.0V (Note) Tamb = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V VCC = 5.5V, SDA = SCL = VCC WP = VSS Conditions
All parameters apply across the specified operating ranges unless otherwise noted. Parameter SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby currentNote: This parameter is periodically sampled and not 100% tested.
Vcc to 5.5V Commercial (C): Industrial (I): Automotive (E): Tamb to +70�C Tamb to +85�C Tamb to +125�C Units kHz ns Remarks All parameters apply across the specified operating ranges unless otherwise noted.
Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free timeSymbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance(Note 2) Time the bus must be free before a new transmission can start (Note 100 pF (Note 3)
ms Byte or Page mode cycles 25�C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.