Homedatasheet24FC515T

24FC515T Datasheet

I2C->64K to 512K
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Description

Features, Applications

Features

Low power CMOS technology - Maximum write current 5.5V - Maximum read current 5.5V - Standby current 100 nA typical 5.5V 2-wire serial interface bus, I2CTM compatible Cascadable for up to four devices Self-timed ERASE/WRITE cycle 64-byte page-write mode available 5 ms max write-cycle time Hardware write protect for entire array Output slope control to eliminate ground bounce Schmitt Trigger inputs for noise suppression 100,000 erase/write cycles Electrostatic discharge protection > 4000V Data retention > 200 years 8-pin PDIP, SOIC packages Temperature ranges: - Industrial (I): to +85�C

Description

The Microchip Technology Inc. 8 (512K bit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range 5.5V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device has both byte-write and page-write capability to 64 bytes of data. This device is capable of both random and sequential reads. Reads may be sequential within address boundaries 8000h to FFFFh. Functional address lines allow up to four devices on the same data bus. This allows for to 2 Mbits total system EEPROM memory. This device is available in the standard 8-pin plastic DIP and SOIC packages.

*24XX515 is used in this document as a generic part number for the 24AA515/24LC515/24FC515 devices.

VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS......................................................................................................... -0.6V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C Soldering temperature of leads (10 seconds)....................................................................................................... +300�C ESD protection on all pins...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

DC CHARACTERISTICS Param. No. D3 D4 VIH VIL VHYS Sym Characteristic A0, A1, SCL, SDA, and WP pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs)

IOL mA @ VCC = 4.5V IOL mA @ VCC = 2.5V VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC VOUT = VSS or VCC = 5.0V (Note) TAMB = 25�C, fC= 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V SCL = SDA = VCC WP = VSS, A2 = VCC

Industrial (I): Characteristic Clock frequency Min. 0.1CB VCC to 5.5V Max. Units kHz TAMB to +85�C Conditions 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) All except, 24FC515 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) (Note 2) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) 1.8V VCC 2.5V VCC 5.5V 2.5V VCC 5.5V (24FC515 only) All except, 24FC515 (Note 1) 24FC515 (Note 1) All except, 24FC515 (Notes 1 and 3) AC CHARACTERISTICS Param. No. 1 Sym FCLK

SDA and SCL rise time (Note 1) SDA and SCL fall time (Note 1)
THD:DAT Data input hold time TSU:DAT Data input setup time

Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum 100 pF Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's website @www.microchip.com.


Features

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