Homedatasheet24LC025-/SN

24LC025-/SN Datasheet

I2C->2K
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Description

Features, Applications

Part VCC Range Number Max Clock Temp. Write Range Protect I Yes 1 8 VCC WP* SCL SDA PDIP, 8-pin SOIC (150 mil), TSSOP and MSOP packages.

FEATURES

Single supply with operation from to 5.5V Low power CMOS technology 1 mA active current typical 1 �A standby current typical at 5.5V Organized as a single block of 128 bytes x 8) Hardware write protection for entire array (24XX024) 2-wire serial interface bus, I2CTM compatible 100 kHz and 400 kHz clock compatibility Page write buffer for to 16 bytes Self-timed write cycle (including auto-erase) 10 ms max. write cycle time Address lines allow up to eight devices on bus 1,000,000 erase/write cycles ESD protection > 4,000V Data retention > 200 years 8-pin PDIP, SOIC, TSSOP and MSOP packages Available for extended temperature ranges - Industrial (I): to +85�C

DESCRIPTION

The Microchip Technology Inc. a 2 Kbit Serial Electrically Erasable PROM with a voltage range to 5.5V. The device is organized as a single block x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 1 �A and 1 mA, respectively. The device has a page write capability for to 16 bytes of data. Functional address lines allow the connection up to eight 24AA024/24LC024/24LC025 devices on the same bus for to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin

SDA SCL VCC VSS Write Protect Circuitry YDEC SENSE AMP R/W CONTROL *WP pin available only on 24XX024. This pin has no internal connection on 24LC025.

Absolute Maximum Ratings VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS......................................................................................................... -0.6V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C ESD protection on all pins..................................................................................................................................................... 4 KV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Function Ground Serial Data Serial Clock to 5.5V Power Supply Chip Selects Hardware Write Protect (24LC024)

VCC to 5.5V Industrial (I): TAMB to +85�C Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Read ICC Write ICCS 0.05 VCC Min. 0.7 VCC Max. 0.3 VCC Units mA �A (Note) IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V VIN WP = VSS VOUT to 5.5V VCC = 5.0V (Note) TAMB = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V VCC = 5.5V, SDA = SCL = VCC WP = VSS, A2 = VSS Conditions

All parameters apply across the specified operating ranges unless otherwise noted. Parameter SCL and SDA pins: High-level input voltage Low-level input voltage Hysteresis of Schmitt trigger inputs Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note:

VCC to 5.5V Industrial (I): TAMB to +85�C Vcc - 5.5V FAST MODE Units Min. Max. kHz ns (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2) (Note 2) Time the bus must be free before a new transmission can start (Note 100 pF All parameters apply across the specified operating ranges unless otherwise noted.

Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time

Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF

TOF ns Output fall time from VIH minimum to VIL maximum CB Input filter spike suppression TSP 50 ns (Note 3) (SDA and SCL pins) Write-cycle time TWC 10 ms Byte or Page mode Endurance 1M cycles 25�C, (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be downloaded at www.microchip.com.


Features

Parameters

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