Homedatasheet24LC256-I/SN

24LC256-I/SN Datasheet

I2C->64K to 512K
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Features
Description

The Microchip Technology Inc. 8 (256 Kbit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range to 5.5 V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability to 64 bytes of data. This device is capable of both random and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the same bus, for to 2 Mbit address space. This device is available in the standard 8-pin plastic DIP, SOIC, TSSOP, MSOP, DFN and 14-lead TSSOP packages.

Low power CMOS technology - Maximum write current V - Maximum read current V - Standby current 100 nA typical V 2-wire serial interface bus, I2C compatible Cascadable for up to eight devices Self-timed ERASE/WRITE cycle 64-byte page-write mode available 5 ms max write-cycle time Hardware write protect for entire array Output slope control to eliminate ground bounce Schmitt trigger inputs for noise suppression 1,000,000 erase/write cycles Electrostatic discharge protection 4000 V Data retention > 200 years 8-pin PDIP, SOIC, TSSOP, MSOP, and DFN packages 14-lead TSSOP package Temperature ranges: - Industrial (I): +85�C - Automotive (E): to +125�C

*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.

VCC............................................................................................................................................................................6.5 V All inputs and outputs w.r.t. VSS....................................................................................................... V to VCC +1.0 V Storage to +150�C Ambient temp. with power to +125�C ESD protection on all pins...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics: Industrial (I): VCC 5.5 V Automotive (E): VCC 5.5 V Characteristic A1, A2, SCL, SDA and WP pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Min 0.7 VCC 0.05 VCC Max 0.3 VCC V CC Units VCC 2.5 V VCC 2.5 V VCC 2.5 V (Note) TAMB to +85�C TAMB to +125�C Conditions

IOL ma @ VCC 4.5 V IOL ma @ VCC 2.5 V VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC VOUT = VSS or VCC 5.0 V (Note) TAMB = 1 MHz VCC 5.5 V, SCL = 400 kHz VCC 5.5 V TAMB to +85�C SCL = SDA = VCC WP = VSS TAMB to +125�C SCL = SDA = VCC WP = VSS

Electrical Characteristics: Industrial (I): VCC 5.5 V Automotive (E): VCC 5.5 V Characteristic Clock frequency Min 0.1CB Max Units kHz TAMB to +85�C TAMB to +125�C Conditions 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC V 24FC256 All except, 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC V 24FC256 (Note 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC 1.8 V VCC 2.5 V VCC 2.5 V VCC V 24FC256 All except, 24FC256 (Note 1) 24FC256 (Note 1) All except, 24FC256 (Notes 1 and 3) 25�C (Note 4)

THD:DAT Data input hold time TSU:DAT Data input setup time

Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum 100 pF Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance

1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model, which can be obtained on Microchip's website: www.microchip.com.


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