Completely implements DDC1TM/DDC2TM interface for monitor identification Hardware write-protect pin Single supply with operation down to 2.5V Low power CMOS technology 1 mA active current typical 10 �A standby current typical 5.5V 2-wire serial interface bus, I2CTM compatible (SCL) Self-timed write cycle (including auto-erase) Page-write buffer for to 8 bytes 100 kHz (2.5V) and 400 kHz (5V) compatibility (SCL) 1,000,000 erase/write cycles guaranteed Data retention > 200 years 8-pin PDIP and SOIC package Available for extended temperature ranges - Commercial to +70�C (C): - Industrial (I) to +85�CDESCRIPTION
The Microchip Technology Inc. x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit Only Mode and bi-directional Mode. Upon power-up, the device will be in the Transmit Only Mode, sending a serial bit stream of the entire memory array contents, clocked by the VCLK pin. A valid high to low transition on the SCL pin will cause the device to enter the bi-directional Mode, with byte selectable read/write capability of the memory array in standard I2C protocol. The 24LCS21 also enables the user to write-protect the entire memory contents using its write-protect pin. The 24LCS21 is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges.
DDC is a trademark of the Video Electronics Standards Association. is a trademark of Philips Corporation.
Function Write Protect (active low) Ground Serial Address/Data I/O Serial Clock (Bi-directional Mode) Serial Clock (Transmit-Only Mode) to 5.5V Power Supply No Connection
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS................-0.6V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C Soldering temperature of leads (10 seconds)............. +300�C ESD protection on all pins.................................................. 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VCC to 5.5V Commercial (C): Tamb to +70�C Industrial (I): Tamb to +85�C Parameter Symbol VIH VIL VIH VIL VHYS VOL1 VOL2 ILI ILO CINT ICC Write ICC Read ICCS Min 0.7 VCC 0.3 VCC 2.0.05 VCC 0.8 0.2 VCC Max Units mA �A VCC 2.7V (Note) VCC < 2.7V (Note) IOL = 3 mA, VCC = 2.5V (Note 1) IOL = 6 mA, VCC = 2.5V VIN 0.1V to VCC VOUT 0.1V to VCC 5.0V (Note1), Tamb = 25�C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC = 5.5V, SDA = SCL = VCC VCLK = VSS Conditions
SCL and SDA pins: High level input voltage Low level input voltage Input levels on VCLK pin: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby currentNote: This parameter is periodically sampled and not 100% tested.
Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free timeFCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Output valid from VCLK high time VCLK low time VCLK setup time VCLK hold time Mode transition time Transmit-Only power up time Input filter spike suppression (VCLK pin) EnduranceTOF TSP TWR TVAA TVHIGH TVLOW TVHST TSPVL TVHZ TVPU TSPV
(Note 2) Time the bus must be free before a new transmission can start (Note 100 pF (Note 3) Byte or Page mode
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.