Homedatasheet24LCS52

24LCS52 Datasheet

I2C->2K
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Features, Applications
Features
Description

The Microchip Technology Inc. a 2 Kbit Electrically Erasable PROM capable of operation across a broad voltage range to 5.5V). This device has a software write protect feature for the lower half of the array, as well as an external pin that can be used to write protect the entire array. The software write protect feature is enabled by sending the device a special command. Once this feature has been enabled, it cannot be reversed. In addition to the software protect feature, there a WP pin that can be used to write protect the entire array, regardless of whether the software write protect register has been written or not. This allows the system designer to protect none, half or all of the array, depending on the application. The device is organized as one block x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 1.8V, with standby and active currents of only 1 �A and 1 mA respectively. The 24XX52 also has a pagewrite capability for to 16 bytes of data. The 24XX52 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP and MSOP packages.

2K I2CTM Serial EEPROM with Software Write Protect

Single supply with operation down to 1.8V Low power CMOS technology 1 mA active current typical 1 �A standby current typical (I-temp) Organized as 1 block of 256 bytes x 8) Software write protection for lower 128 bytes Hardware write protection for entire array 2-wire serial interface bus, I2CTM compatible Schmitt trigger inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz (24AA52) and 400 kHz (24LCS52) compatibility Self-timed write cycle (including auto-erase) Page-write buffer for to 16 bytes 3.5 ms typical write cycle time for page-write ESD protection 4,000V 1,000,000 erase/write cycles Data retention > 200 years 8-lead PDIP, SOIC, TSSOP and MSOP package Available for extended temperature ranges: - Industrial (I): to +85�C

WP HV Generator Software write protected area (00h-7Fh) Standard Array

Part Number 24AA52 24LCS52 VCC Range 1.8-5.5 2.5-5.5 Max Clock Frequency kHz(1) 400 kHz Temp Ranges I

Write Protect Circuitry YDEC SENSE AMP R/W CONTROL
*24XX52 is used in this document as a generic part number for the 24AA52/24LCS52 devices.

VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS......................................................................................................... -0.3V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C ESD protection on all pins...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

VCC to +5.5V Industrial (I): TAMB to +85�C Min 0.7 VCC 0.05 VCC Standby current Typ 0.20 0.36 Max 0.3 VCC Units �A 0.2 VCC for VCC < 2.5V (Note) IOL = 3.0 mA, VCC = 2.5V VIN 0.1V to VCC VOUT 0.1V to VCC = 5.0V (Note) TAMB = 25�C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz Industrial SDA = SCL = VCC V SS Conditions

DC CHARACTERISTICS Param. Symbol No. D10 D11 VIH VIL VHYS VOL ILI ILO CIN, COUT ICC read ICCS Characteristic A1, A2, SCL, SDA and WP pins High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs)

VCC to +5.5V Industrial (I): TAMB to +85�C Min Typ Max Units kHz ns Conditions 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC 2.5V (24AA52) (Note 1) 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC 2.5V (24AA52) (Note 2) 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC (24AA52) 2.5V VCC 5.5V 1.8V VCC 2.5V (24AA52)

AC CHARACTERISTICS Param. Symbol No. FCLK THIGH TLOW TR TF Characteristic Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time

THD:STA START condition hold time TSU:STA START condition setup time
THD:DAT Data input hold time TSU:DAT Data input setup time

TSU:STO STOP condition setup time TAA TBUF Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance

Note 1: Not 100% tested. B = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and V HYS specifications are due to new Schmitt trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's website: www.microchip.com.


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