3D7501D Datasheet

Protocol Controllers


Features, Applications


All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Maximum data rate: 50 MBaud

The is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single biphase-level signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ). All pins marked N/C must be left unconnected.

DAT CLK RESB TX TXB VCC GND Data Input Clock Input Reset Signal Output Inverted Signal Output +5 Volts Ground

The all-CMOS 3D7501 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Encoder. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14pin SOICs.

The 3D7501 Manchester Encoder samples the data input at the rising edge of the input clock. The sampled data is used in conjunction with the clock rising and falling edges to generate the byphase level Manchester code.

The 3D7501 presents at its outputs the true and the complimented encoded data. The High-to-Low time skew of the selected data output should be budgeted by the user, as it relates to his application, to satisfactorily estimate the distortion of the transmitted data stream. Such estimate is very useful in determining the functionality and margins of the data link, a 3D7502 Manchester Decoder is used to decode the received data.

The 3D7501 Manchester Encoder inputs are TTL compatible. The user should assure himself that the 1.5 volt TTL threshold is used when referring to all timing, especially to the input clock duty cycle.

The 3D7501 Manchester Encoder employs the timing of the clock rising and falling edges (duty cycle) to implement the required coding scheme. To reduce the difference between the output data high time and low time, it is essential that the deviation of the input clock duty cycle from 50/50 be minimized.

CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D7501 Manchester encoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature.

Power-on reset (Left high for normal operation)

PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN MAX 150 300 UNITS mA C NOTES

to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL & TF MIN MAX 40 UNITS mA ns NOTES

*IDD(Dynamic) 2 * CLD * VDD * F where: CLD = Average capacitance load/pin (pf) F = Input frequency (GHz)

Input Capacitance 10 pf typical Output Load Capacitance (CLD) 25 pf max

to 5.25V) PARAMETER Input Baud Rate Clock Frequency Data set-up to clock rising Data hold from clock rising TX High-Low time skew TXB High-Low time skew TX - TXB High/Low time skew

Notes: 1: Assumes a 50% duty cycle clock input



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