TMOS is a new technology designed to achieve an on�resistance area product about one�half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E�FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
New Features of TMOS V On�resistance Area Product about One�half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than E�FET Predecessors
Features Common to TMOS V and TMOS E�FETS Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS E�FET MAXIMUM RATINGS (TC = 25�C unless otherwise noted)
Rating Drain�to�Source Voltage Drain�to�Gate Voltage (RGS 1.0 M) Gate�to�Source Voltage Continuous Gate�to�Source Voltage Non�repetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100�C Drain Current Single Pulse (tp 10 �s) Total Power Dissipation Derate above 25�C Operating and Storage Temperature Range Single Pulse Drain�to�Source Avalanche Energy Starting = 25�C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak = 15 Apk, = 1.0 mH, 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
Designer's Data for "Worst Case" Conditions The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves representing boundaries on device characteristics are given to facilitate "worst case" design.
E�FET, Designer's, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Characteristic OFF CHARACTERISTICS Drain�to�Source Breakdown Voltage (VGS = 0 Vdc, = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, = 150�C) Gate�Body Leakage Current (VGS � 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, = 250 �Adc) Threshold Temperature Coefficient (Negative) Static Drain�to�Source On�Resistance (VGS = 5.0 Vdc, = 7.5 Adc) Drain�to�Source On�Voltage (VGS = 5.0 Vdc, = 15 Adc) (VGS = 5.0 Vdc, = 7.5 Adc, = 150�C) Forward Transconductance (VDS = 8.0 Vdc, = 7.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn�On Delay Time Rise Time Turn�Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, = 15 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, = 15 Adc, VGS = 5.0 Vdc, 9.1 ) td(on) tr td(off) Q2 Q3 SOURCE�DRAIN DIODE CHARACTERISTICS Forward On�Voltage (1) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, = 150�C) VSD trr (IS = 15 Adc, VGS = 0 Vdc, dIS/dt = 100 A/�s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die.) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 �s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. (3) Reflects typical values. Max limit � Typ Cpk 3 x SIGMA ta tb QRR �C ns Vdc nC ns (VDS = 25 Vdc, VGS = 0 Vdc, = 1.0 MHz) Ciss Coss Crss pF (Cpk 2.0) (3) VGS(th) 1.0 (Cpk 2.0) (3) RDS(on) VDS(on) gFS mhos 0.075 0.085 Vdc 4.0 2.0 Vdc mV/�C Ohm (Cpk 2.0) (3) V(BR)DSS 60 IDSS IGSS 10 100 nAdc 68 Vdc mV/�C �Adc Symbol Min Typ Max UnitMotorola TMOS Power MOSFET Transistor Device Data
R DS(on) , DRAIN�TO�SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN�TO�SOURCE RESISTANCE (OHMS)
Figure 3. On�Resistance versus Drain Current and Temperature
Figure 4. On�Resistance versus Drain Current and Gate Voltage
Figure 6. Drain�To�Source Leakage Current versus Voltage