Homedatasheet49FCT806

49FCT806 Datasheet

Dual 1:5 Inverting Clock Driver W/cmos Outputs
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Description

Features, Applications

0.5 MICRON CMOS Technology Guaranteed low skew < 700ps (max.) Low duty cycle distortion < 1ns (max.) Low CMOS power levels TTL compatible inputs and outputs Rail-to-rail output voltage swing High drive: -24mA IOH, +64mA IOL Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output Available in SSOP and SOIC packages

The is an inverting buffer/clock driver built using advanced dual metal CMOS technology. Each bank consists of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. These devices feature a "heart-beat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT806 offers low capacitance inputs and hysteresis. Rail-to-rail output swing improves noise margin and allows easy interface with CMOS inputs.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Symbol Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max to +120 Unit �C mA

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Input and VCC terminals. 3. Output and I/O terminals.

Symbol CIN C OUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. 6 8 Unit pF

NOTE: 1. This parameter is measured at characterization but not tested. NOTE: 1. Pin 8 is not internally connected on devices with a "K" prefix in the date code. On older devices, pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level.

Pin Names OEA, OEB INA, INB OAn, OBn MON Clock Inputs Clock Outputs Monitor Output Description 3-State Output Enable Inputs (Active LOW)

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: to +70�C, VCC � 5%

Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VOH Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IIN = �18mA VCC = Max., = GND(3) VCC = 3V, VIN = VLC or VHC VCC = Min. VIN = VIH or VIL VCC = 3V, VIN = VLC or VHC VOL VH ICC Output LOW Voltage Input Hysteresis for all inputs Quiescent Power Supply Current VCC = Min. VIN = VIH or VIL Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Off State (Hi-Z) Output Current Test Conditions(1)

Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max.

NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc 5V, +25�C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.


Features

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Manufacturer information

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