Homedatasheet4LVC652PWDH

4LVC652PWDH Datasheet

Octal Transceiver/register With Dual Enable 3-state
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Description

Features, Applications

Product specification Supercedes data of 1993 Dec 01 IC24 Data Handbook 1998 Jul 29

Wide supply voltage range 3.6V In accordance with JEDEC standard no. 8-1A CMOS low power consumption Direct interface with TTL levels 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic

DESCRIPTION

The is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.

The 74LVC652 consist of 8 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the `A' or `B' or both buses, will be stored in the internal registers, at the appropriate clock inputs (CPAB or CPBA) regardless of the select inputs (SAB and SBA) or output enable (OEAB and OEBA) control inputs. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the OEn inputs this operating mode permits. The output enable inputs OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from Bn is possible and when OEBA is HIGH, there is no data transmission from to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input.

GND = 0V; Tamb v2.5 ns SYMBOL PARAMETER tPHL/tPLH fmax CI CPD Propagation delay An to Bn; to An Maximum clock frequency Input capacitance Power dissipation capacitance per latch Notes 1, 2 CONDITIONS = 50pF VCC = 3.3V TYPICAL UNIT ns MHz pF

NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in �W) fi ) (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition VI = GND to VCC.

PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE to +85�C OUTSIDE NORTH AMERICA 74LVC652 PW NORTH AMERICA 4LVC652PW DH PKG. DWG. SOT340-1 SOT355-1

PIN NUMBER 1 SYMBOL CPAB SAB OEAB to A7 GND to B7 OEBA SBA CPBA VCC FUNCTION `A' to `B' clock input (LOW-to-HIGH, edge-triggered) Select `A' to `B' source input Output enable to A input (active LOW) `A' data inputs/outputs Ground (0V) `B' data inputs/outputs Output enable to B input Select `B' to `A' source input `B' to `A' clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage

INPUTS OEAB OEBA CPAB or L CPBA or L SAB SBA DATA I/O to A7 input un * output input output to B7 input un * output input output FUNCTION isolation store A and B data store A, hold B, store A in both registers hold A, store B, store B in both registers real-time B data to A bus stored B data to A bus real-time A data to B bus stored A data to B bus stored A data to B bus and stored B data to A bus

The data output functions may be enabled or disabled by various signals at the OEAB and OEBA inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. = unspecified = HIGH voltage level = LOW voltage level = Don't care = LOW�to�HIGH level transition


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