Homedatasheet5474FMQB

5474FMQB Datasheet

Dual Positive-edge-triggered D Flip-flops With Preset, Clear And Complementary Outputs
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Description

Features, Applications
DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs
DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs

Features

Alternate Military Aerospace device (5474) is available Contact a National Semiconductor Sales Office Distributor for specifications

H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level e Positive-going transition of the clock e This configuration is nonstable that is it will not persist when either the preset and or clear inputs return to their inactive (high) level Q0 e The output logic level of Q before the indicated input conditions were established

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage 5 5V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings The ``Recommended Operating Conditions'' table will define the conditions for actual device operation

Operating Free Air Temperature Range C DM54 and 70 C Storage Temperature Range

Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 2) Pulse Width (Note 2) Clock High Clock Low Clear Low Preset Low tSU tH TA Input Setup Time (Notes 1 Input Hold Time (Notes 20u 5u

u) indicates the rising edge of the clock pulse is used for reference

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage Max Conditions VCC e Min b12 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max 5 5V VCC e Max 4V D Clock Clear Preset IIL Low Level Input Current VCC e Max 0 4V (Note 6) D Clock Clear Preset IOS ICC Short Circuit Output Current Supply Current VCC e Max (Note DM54 DM74

Note 3 All typicals are at VCC 25 C Note 4 Not more than one output should be shorted at a time Note 5 With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded Note 6 Clear is tested with preset high and preset is tested with clear high

Switching Characteristics at VCC e 5V and 25 C (See Section 1 for Test Waveforms and Output Load)

Symbol Parameter From (Input) To (Output) Min fMAX tPHL tPLH tPHL tPLH tPHL tPLH Maximum Clock Frequency Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Preset to Q Preset to Q Clear to Q Clear to Q Clock or Q Clock 15 pF Max MHz ns Units


Features

Parameters

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Manufacturer information

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