|54ABT573 Octal D-Type Latch with TRI-STATE Outputs
54ABT573 Octal D-Type Latch with TRI-STATE � Outputs
The is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the 'ABT373 but has different pinouts. n Functionally identical 'ABT373 n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability mA n Output switching specified for both 50 pF and 250 pF loads n Guaranteed latchup protection n High impedance glitch-free bus loading during entire power up and power down n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321901Features
n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Useful as input or output port for microprocessors
Military 54ABT573W-QML 54ABT573E-QML Package Number E20A 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package DescriptionDescription
Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation.
The 'ABT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. OE
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature to +150�C Ambient Temperature under Bias to +125�C Junction Temperature under Bias Ceramic to +175�C VCC Pin Potential to Ground Pin to +7.0V Input Voltage (Note to +7.0V Input Current (Note +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State +5.5V in the HIGH State -0.5V to VCC Current Applied to Output in LOW State (Max) Twice the rated IOL (mA) DC Latchup Source Current -500 mA
Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input to +5.5V (V/t) 50 mV/ns 20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE ICCD Dynamic ICC (Note 4) No Load �A mA mA/ MHz Max - 5.5V Max 0.0 Max �A Max VIN = 0.5V (Note 4) VIN = 0.0V IID 1.9 �A All Other Pins Grounded VOUT = 2.0V VOUT = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OE = VCC All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs Open OE = GND, LE = VCC (Note 3) One Bit Toggling, 50% Duty CycleNote 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed but not tested.
Conditions Recognized HIGH Signal Recognized LOW Signal