Homedatasheet54ABT574

54ABT574 Datasheet

Military/Aerospace->ABT
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Description

Features, Applications
54ABT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
54ABT574 Octal D-Type Flip-Flop with TRI-STATE � Outputs

The is an octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. The device is functionally identical to the 'ABT374 except for the pinouts. n TRI-STATE outputs for bus-oriented applications n Output sink capability of 48 mA, source capability mA n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching, noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9322001

Features

n Inputs and outputs on opposite sides of package allowing easy interface with microprocessors n Useful as input or output port for microprocessors n Functionally identical to 'ABT374

Military 54ABT574W/883 54ABT574E/883 Package Number E20A 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description 20-Lead Ceramic Dual-In-Line

Pin Names OE O0�O7 Data Inputs Clock Pulse Input (Active Rising Edge) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Outputs Description

FAST � and TRI-STATE � are registered trademarks of National Semiconductor Corporation.

The 'ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops. OE

Data Available Data Available No Change in Data No Change in Data

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition = No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current -0.5V to VCC twice the rated IOL (mA) -500 mA

Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input to +5.5V (V/t) 50 mV/ns 20 mV/ns 100 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE ICCD Dynamic ICC (Note 4)

Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested.

Recognized LOW Signal IIN -18 mA IOH -3 mA IOH -24 mA IOL 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID 1.9 �A All Other Pins Grounded VOUT = 2.0V VOUT = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Other GND All Outputs HIGH All Outputs LOW OE = VCC All Others at VCC or GND VI = VCC - 2.1V

Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs Open, OE = GND, One Bit Toggling (Note 3), 50% Duty Cycle


Features

Parameters

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