54AC74L Datasheet

Dual D-type Positive Edge-triggered Flip-flop


Features, Applications

The is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH


ICC reduced by 50% Output source/sink mA 'ACT74 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 'ACT74: 5962-87525

Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
FACT is a registered trademark of Fairchild Semiconductor Corporation.

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP -0.5V to VCC -0.5V to VCC + 0.5V

Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from to 2.0V VCC 0V to VCC 0V to VCC to +125�C

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT � circuits outside databook specifications.

Symbol Parameter VCC (V) to +125�C Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage (Note 2) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage (Note 2) VIN = VIL or VIH 4.5 5.5 IIN Maximum Input Leakage Current V �A IOL VI = VCC, GND V IOH -24 mA IOUT �A V IOUT �A V VOUT 0.1V or VCC 0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions



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