Members of the Texas Instruments Widebus TM Family Inputs Are TTL-Voltage Compatible Parity Error Flag With Parity Generator/Checker Register for Storage of the Parity Error Flag Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-�m Process 500-mA Typical Latch-Up Immunity at 125�C Package Options Include 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacingsdescription
The 'ACT16833 consist of two noninverting to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin or 2PARITY). When data is transmitted from the B bus to the A bus, 2PARITY is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.
The error or 2ERR) output is configured as an open-collector output. The B-to-A parity error flag is clocked into 2ERR on the low-to-high transition of the clock or 2CLK) input. 2ERR is cleared (set high) by taking the clear or 2CLR) input low. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. The 74ACT16833 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16833 is characterized for operation over the full military temperature range to 125�C. The 74ACT16833 is characterized for operation from to 85�C.
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FUNCTION TABLE INPUTS OEB H X OEA L X CLR CLK OF H Odd Even NA X Odd Even Odd Even H NA Odd Even B X OUTPUT AND I/O A NA PARITY H NA ERR NA A data to B bus and generate inverted parity Isolation� FUNCTION A data to B bus and generate parity B data to A bus and check parity Check error-flag register
NA = not applicable, = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume ERR was previously high. � In this mode, ERR (when clocked) shows inverted parity of the A bus.This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.