54ACT258F Datasheet

Quad 2-input Multiplexer With Tri-state Outputs


Features, Applications

The is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems. Multiplexer expansion by tying outputs together Inverting TRI-STATE outputs Outputs source/sink mA 'ACT258 has TTL-compatible inputs Standard Military Drawing (SMD) 'AC258: 5962-91604


Description Common Data Select Input TRI-STATE Output Enable Input Data Inputs from Source 0 Data Inputs from Source 1 TRI-STATE Inverting Data Outputs

TRI-STATE is a registered trademark of National Semiconductor Corporation. FACT is a registered trademark of Fairchild Semiconductor Corporation.

The is a quad 2-input multiplexer with TRI-STATE outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The 'AC/'ACT258 is the logic implementation 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Za = OE Zb = OE Zc = OE Zd = OE I0d S) When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs of the TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so there is no overlap.

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.



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