Homedatasheet54ACT283FMQB

54ACT283FMQB Datasheet

Military/Aerospace->FACT ACT
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Description

Features, Applications
54ACT283 4-Bit Binary Full Adder with Fast Carry

The 'ACT283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words (A0�A3, B0�B3) and a Carry input (C0). It generates the binary Sum outputs (S0�S3) and the Carry output (C4) from the most significant bit. The 'ACT283 will operate with either active HIGH or active LOW operands (positive or negative logic).

Features

Guaranteed 4000V minimum ESD protection Outputs source/sink 24 mA TTL-compatible inputs Available to Mil-Std-883

The 'ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0�S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. + 16C4 Where = plus

Interchanging inputs of equal weight does not affect the operation. Thus A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 'ACT283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1. Note that C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the 'ACT283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 'ACT283 into a 2-bit and a 1-bit adder. The third stage adder S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2.

Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are

equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1�I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I1�I5 are true, the output M5 is true.

FIGURE 1. Active HIGH versus Active LOW Interpretation

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.


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