54ACTQ273F Datasheet

Quiet Series Octal D Flip-flop


Features, Applications

The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance.


n ICC reduced 50% n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Buffered common clock and asynchronous master reset n Outputs source/sink mA n Faster prop delays than the standard 4 kV minimum ESD immunity n Standard Microcircuit Drawing (SMD) 5962-89735

Description Data Inputs Master Reset Clock Pulse Input Data Outputs

GTOTM is a trademark of National Semiconductor Corporation. FACT is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet SeriesTM is a trademark of Fairchild Semiconductor Corporation.

Operating Mode MR Reset (Clear) Load "1" Load "0"

Note H = HIGH Voltage Level Note L = LOW Voltage Level Note X = Immaterial Note N = LOW-to-HIGH Transition

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) -0.5V to VCC -0.5V to VCC + 0.5V

DC Latch-up Source or Sink Current Junction Temperature (TJ) CDIP

Supply Voltage (VCC) 'ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate V/t 'ACTQ Devices VIN from to 2.0V VCC 0V to VCC 0V to VCC to +125�C

Note 5: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT � circuits outside databook specifications. Note 6: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from to +125�C.

Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage to +125�C Guaranteed Limits (Note 7) VIN = VIL or VIH IOH -24 mA IOH -24 mA IOUT 50 �A (Note 7) VIN = VIL or VIH IOL 24 mA IOL VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND (Note 9) V VOUT 0.1V or VCC - 0.1V VOUT 0.1V or VCC - 0.1V IOUT -50 �A Units Conditions

4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 8) Maximum Quiescent Supply Current



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