54ACTQ543LMQBD Datasheet

Quiet Series Octal Registered Transceiver With Tri-state Outputs


Features, Applications
54ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs
54ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE � Outputs

The is a non-inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance.


n Guaranteed simultaneous switching noise level and dynamic threshold performance n 8-bit octal latched transceiver n Separate controls for data flow in each direction n Back-to-back registers for storage n Outputs source/sink 4 kV minimum ESD immunity

Military 54ACTQ543FMQB 54ACTQ543LMQB Package Number W24C E28A Package Description 24-Lead Ceramic Dual-In-Line 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier, Type C IEEE/IEC

GTOTM is a trademark of National Semiconductor Corporation. TRI-STATE is a registered trademark of National Semiconductor Corporation. FACT is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet SeriesTM is a trademark of Fairchild Semiconductor Corporation.


Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A TRI-STATE Outputs B-to-A Data Inputs or A-to-B TRI-STATE Outputs

The ACTQ543 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0�A7 or take data from B0�B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the TRI-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from A is similar, but using the CEBA, LEBA and OEBA inputs.

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.



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