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The a 4-bit Arithmetic logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations is 40% faster than the Schottky ALU and only consumes 30% as much power FeaturesFull lookahead for high-speed arithmetic operation on long words Guaranteed 4000V minimum ESD protection Package Description (0 600 Wide) Molded Dual-In-Line (0 300 Wide) Molded Dual-In-Line 24-Lead Ceramic Dual-In-Line 300 ) Ceramic Dual-In-Line 300 ) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCXNote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation 9491 RRD-B30M105 Printed S A A Operand Inputs (Active LOW) B Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output The a 4-bit high-speed parallel Arithmetic Logic Unit (ALU) Controlled by the four Function Select inputs � S3) and the Mode Control input (M) it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands The Function Table lists these operations When the Mode Control input (M) is HIGH all internal carries are inhibited and the device performs logic operations on the individual bits as listed When the Mode Control input is LOW the carries are enabled and the device performs arithmetic operations on the two 4-bit words The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the a 4 output or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate) In the Add mode P indicates that 15 or more while G indicates that 16 or more In the Subtract mode P indicates that F is zero or less while G indicates that F is less than zero P and G are not affected by carry in When speed requirements are not stringent the 'F181 can be used in a simple Ripple Carry mode by connecting the Carry output (Cn a 4) signal to the Carry input (Cn) of the next unit For high speed operation the device is used in conjunction with a carry lookahead circuit One carry lookahead package is required for each group of four 'F181 devices Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths The e B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode The e B output is open collector and can be wired AND with other e B outputs to give a comparison for more than four bits The e B signal can also be used with the a 4 signal to indicate AlB and AkB The Function Table lists the arithmetic operations that are performed without a carry in An incoming carry adds a one to each operation Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied Because subtraction is actually performed by complementary addition (1s complement) a carry out means borrow thus a carry is generated when there is no underflow and no carry is generated when there is underflow As indicated this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs For either case the table lists the operations that are performed to the operands labeled inside the logic symbol S2 S3 Logic A AB AaB Logic ``1'' AaB B AZB AaB AB AZB B AaB Logic AB A AaB AB Logic AB B AZB AB AaB AZB B AB Logic ``1'' AaB A AaB AB Logic AB B AZB AaB AZB B AaB Logic A AB AaB Logic ``0'' AaB B AZB AB AZB B AB Logic ``1'' AaB A Arithmetic C0 e Inactive) A minus A B minus A B minus 1 minus 1 (2s comp ) A plus A B plus B) A minus B minus 1 AaB A plus B) A plus A B plus a B) AaB A plus A) A plus B A plus AaB minus 1 (2s comp ) A plus A B plus B) A minus B minus A B minus 1 A plus B A plus A B plus A B minus 1 A plus A) A plus B) A plus B) A minus 1 A minus A B minus A B minus 1 minus 1 (2s comp ) A plus A B plus B) A plus B AaB A plus B) A minus B minus A B plus a B) AaB A plus A) A plus B A plus AaB minus 1 (2s comp ) A plus B) A plus A B minus 1 A plus B A minus B minus A B plus A B minus 1 A plus A) A plus B) A plus B) A minus 1 Arithmetic C0 e Active) A AB Zero A plus a B) plus A B plus a B) plus 1 A minus plus 1 A plus a B plus 1 A plus B plus A B plus a B) plus 1 A plus c A) plus 1 A plus A B plus 1 A plus A B plus 1 A plus 1 A plus 1 Zero A plus A B plus A B plus a B) plus 1 A minus AB A plus A B plus 1 A plus B plus A B plus a B) plus AB A plus c A) plus 1 A plus a B) plus 1 A plus a B) plus A AB Zero A plus a B) plus A B plus a B) plus 1 A plus B plus 1 A plus a B) plus 1 A minus A B plus a B) plus 1 A plus c A) plus 1 A plus A B plus 1 A plus A B plus 1 A plus 1 A plus 1 Zero A plus A B plus A B plus a B) plus 1 A plus B plus AB A plus A B plus 1 A minus A B plus a B) plus AB A plus c A) plus 1 A plus a B) plus 1 A plus a B) plus 1 A c A Input Data Inverted B Input Data Trued A Input Data True B Input Date Inverted |

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