54F194DM Datasheet



Features, Applications

The is a high-speed 4-bit bidirectional universal shift register As a high-speed multifunctional sequential building block it is useful in a wide variety of applications It may be used in serial-serial shift left shift right serial-parallel parallel-serial and parallel-parallel data register transfers The 'F194 is similar in operation to the 'F195 universal shift register with added features of shift left without external connections and hold (do nothing) modes of operation


Typical shift frequency of 150 MHz Asynchronous master reset Hold (do nothing) mode Fully synchronous serial or parallel data transfers

Package Description (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line (0 150 Wide) Molded Small Outline JEDEC (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C

Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation 9498 RRD-B30M105 Printed S A

Pin Names � P3 DSR DSL 54F 74F Description Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs UL HIGH LOW Input IIH IIL Output IOH IOL 20 mA

The 'F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right shift left parallel load and hold operations Signals applied to the Select (S0 S1) inputs determine the type of operation as shown in the Mode Select Table Signals on the Select Parallel data � P3) and Serial data (DSR DSL) inputs can change when the clock is in either state provided only that the recommended setup and hold times with respect to the clock rising edge are observed A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW

Mode Select Table Operating Mode Reset Hold Shift Left Shift Right Parallel Load

H (h) e High Voltage Level L (l) e Low Voltage Level pn (qn) e Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition X e Immaterial

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max)

Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs

Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current

Conditions Recognized as a HIGH Signal Recognized as a LOW Signal

IIN b18 mA IOH b1 mA IOH b1 mA IOH b1 mA IOL 20 mA IOL 20 mA VIN 2 7V VIN 7 0V VOUT e VCC IID 9 mA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN 0 5V VOUT e 0V



Manufacturer information

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