Homedatasheet54F299FM

54F299FM Datasheet

Octal Universal Shift/storage Register With Common Parallel I/o Pins
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Description

Features, Applications
54F 74F299 Octal Universal Shift Storage Register with Common Parallel I O Pins

The an 8-bit universal shift storage register with TRI-STATE outputs Four modes of operation are possible hold (store) shift left shift right and load data The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins Additional outputs � Q7 are provided to allow easy serial cascading A separate active LOW Master Reset is used to reset the register

Features

Common parallel I O for reduced pin count Additional serial inputs and outputs for expansion Four operating modes shift left shift right load and store TRI-STATE outputs for bus-oriented applications Guaranteed 4000V minimum ESD protection

Package Description (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C

Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs

The 'F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left shift right parallel load and hold operations The type of operation is determined by S0 and S1 as shown in the Mode Select Table All flip-flop outputs are brought out through TRI-STATE buffers to separate I O pins that also serve as data inputs in the parallel load mode Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops All other state changes are initiated by the rising edge of the clock Inputs can change when the clock is in either state provided only that the recommended setup and hold times relative to the rising edge of CP are observed A HIGH signal on either or OE2 disables the TRISTATE buffers and puts the I O pins in the high impedance state In this condition the shift hold load and reset operations can still occur The TRI-STATE outputs are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation Mode Select Table Inputs S0 CP Asynchronous Reset �Q7 e LOW H L Parallel Load H L Shift Right x Q1 etc H L Shift Left x Q6 etc L X Hold Response

H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays


Features

Parameters

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Manufacturer information

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